> sim RTL

ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 18:31:48  up  21:29,  2 users,  load average: 1.18, 0.83, 0.63

npc/csrc/main.cpp

@@ -1,11 +1,21 @@
+#include <cstdlib>
+#include <cassert>
+#include <cstdlib>
 #include "Vexample.h"
 #include "verilated.h"
 
 int main(int argc, char **argv, char **env) {
     Verilated::commandArgs(argc, argv);
     Vexample *top = new Vexample;
-    while (!Verilated::gotFinish()) {
+    int round = 100;
+    while (round--) {
+        int a = rand() & 1;
+        int b = rand() & 1;
+        top->a = a;
+        top->b = b;
         top->eval();
+        printf("a = %d, b = %d, f = %d\n", a, b, top->f);
+        assert(top->f == (a ^ b));
     }
     exit(0);
 }

npc/obj/Vexample.cpp

@@ -9,6 +9,9 @@
 Vexample::Vexample(VerilatedContext* _vcontextp__, const char* _vcname__)
     : VerilatedModel{*_vcontextp__}
     , vlSymsp{new Vexample__Syms(contextp(), _vcname__, this)}
+    , a{vlSymsp->TOP.a}
+    , b{vlSymsp->TOP.b}
+    , f{vlSymsp->TOP.f}
     , rootp{&(vlSymsp->TOP)}
 {
     // Register model with the context

npc/obj/Vexample.h

@@ -24,6 +24,9 @@ class alignas(VL_CACHE_LINE_BYTES) Vexample VL_NOT_FINAL : public VerilatedModel
     // PORTS
     // The application code writes and reads these signals to
     // propagate new values into/out from the Verilated model.
+    VL_IN8(&a,0,0);
+    VL_IN8(&b,0,0);
+    VL_OUT8(&f,0,0);
 
     // CELLS
     // Public to allow access to /* verilator public */ items.

npc/obj/Vexample__ALL.cpp

@@ -4,5 +4,6 @@
 #include "Vexample___024root__DepSet_h625e39dc__0.cpp"
 #include "Vexample___024root__DepSet_hcb5acca5__0.cpp"
 #include "Vexample___024root__Slow.cpp"
+#include "Vexample___024root__DepSet_h625e39dc__0__Slow.cpp"
 #include "Vexample___024root__DepSet_hcb5acca5__0__Slow.cpp"
 #include "Vexample__Syms.cpp"

npc/obj/Vexample___024root.h

@@ -14,8 +14,15 @@ class alignas(VL_CACHE_LINE_BYTES) Vexample___024root final : public VerilatedMo
   public:
 
     // DESIGN SPECIFIC STATE
+    VL_IN8(a,0,0);
+    VL_IN8(b,0,0);
+    VL_OUT8(f,0,0);
+    CData/*0:0*/ __VstlFirstIteration;
+    CData/*0:0*/ __VicoFirstIteration;
     CData/*0:0*/ __VactContinue;
     IData/*31:0*/ __VactIterCount;
+    VlTriggerVec<1> __VstlTriggered;
+    VlTriggerVec<1> __VicoTriggered;
     VlTriggerVec<0> __VactTriggered;
     VlTriggerVec<0> __VnbaTriggered;
 

npc/obj/Vexample___024root__DepSet_h625e39dc__0.cpp

@@ -6,6 +6,23 @@
 #include "Vexample__Syms.h"
 #include "Vexample___024root.h"
 
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vexample___024root___dump_triggers__ico(Vexample___024root* vlSelf);
+#endif  // VL_DEBUG
+
+void Vexample___024root___eval_triggers__ico(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_triggers__ico\n"); );
+    // Body
+    vlSelf->__VicoTriggered.set(0U, (IData)(vlSelf->__VicoFirstIteration));
+#ifdef VL_DEBUG
+    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
+        Vexample___024root___dump_triggers__ico(vlSelf);
+    }
+#endif
+}
+
 #ifdef VL_DEBUG
 VL_ATTR_COLD void Vexample___024root___dump_triggers__act(Vexample___024root* vlSelf);
 #endif  // VL_DEBUG

npc/obj/Vexample___024root__DepSet_h625e39dc__0__Slow.cpp

@@ -0,0 +1,24 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vexample.h for the primary calling header
+
+#include "Vexample__pch.h"
+#include "Vexample__Syms.h"
+#include "Vexample___024root.h"
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vexample___024root___dump_triggers__stl(Vexample___024root* vlSelf);
+#endif  // VL_DEBUG
+
+VL_ATTR_COLD void Vexample___024root___eval_triggers__stl(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_triggers__stl\n"); );
+    // Body
+    vlSelf->__VstlTriggered.set(0U, (IData)(vlSelf->__VstlFirstIteration));
+#ifdef VL_DEBUG
+    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
+        Vexample___024root___dump_triggers__stl(vlSelf);
+    }
+#endif
+}

npc/obj/Vexample___024root__DepSet_hcb5acca5__0.cpp

@@ -5,6 +5,41 @@
 #include "Vexample__pch.h"
 #include "Vexample___024root.h"
 
+VL_INLINE_OPT void Vexample___024root___ico_sequent__TOP__0(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___ico_sequent__TOP__0\n"); );
+    // Body
+    vlSelf->f = ((IData)(vlSelf->a) ^ (IData)(vlSelf->b));
+}
+
+void Vexample___024root___eval_ico(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_ico\n"); );
+    // Body
+    if ((1ULL & vlSelf->__VicoTriggered.word(0U))) {
+        Vexample___024root___ico_sequent__TOP__0(vlSelf);
+    }
+}
+
+void Vexample___024root___eval_triggers__ico(Vexample___024root* vlSelf);
+
+bool Vexample___024root___eval_phase__ico(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_phase__ico\n"); );
+    // Init
+    CData/*0:0*/ __VicoExecute;
+    // Body
+    Vexample___024root___eval_triggers__ico(vlSelf);
+    __VicoExecute = vlSelf->__VicoTriggered.any();
+    if (__VicoExecute) {
+        Vexample___024root___eval_ico(vlSelf);
+    }
+    return (__VicoExecute);
+}
+
 void Vexample___024root___eval_act(Vexample___024root* vlSelf) {
     if (false && vlSelf) {}  // Prevent unused
     Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
@@ -52,6 +87,9 @@ bool Vexample___024root___eval_phase__nba(Vexample___024root* vlSelf) {
     return (__VnbaExecute);
 }
 
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vexample___024root___dump_triggers__ico(Vexample___024root* vlSelf);
+#endif  // VL_DEBUG
 #ifdef VL_DEBUG
 VL_ATTR_COLD void Vexample___024root___dump_triggers__nba(Vexample___024root* vlSelf);
 #endif  // VL_DEBUG
@@ -64,9 +102,28 @@ void Vexample___024root___eval(Vexample___024root* vlSelf) {
     Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval\n"); );
     // Init
+    IData/*31:0*/ __VicoIterCount;
+    CData/*0:0*/ __VicoContinue;
     IData/*31:0*/ __VnbaIterCount;
     CData/*0:0*/ __VnbaContinue;
     // Body
+    __VicoIterCount = 0U;
+    vlSelf->__VicoFirstIteration = 1U;
+    __VicoContinue = 1U;
+    while (__VicoContinue) {
+        if (VL_UNLIKELY((0x64U < __VicoIterCount))) {
+#ifdef VL_DEBUG
+            Vexample___024root___dump_triggers__ico(vlSelf);
+#endif
+            VL_FATAL_MT("vsrc/example.v", 1, "", "Input combinational region did not converge.");
+        }
+        __VicoIterCount = ((IData)(1U) + __VicoIterCount);
+        __VicoContinue = 0U;
+        if (Vexample___024root___eval_phase__ico(vlSelf)) {
+            __VicoContinue = 1U;
+        }
+        vlSelf->__VicoFirstIteration = 0U;
+    }
     __VnbaIterCount = 0U;
     __VnbaContinue = 1U;
     while (__VnbaContinue) {
@@ -105,5 +162,10 @@ void Vexample___024root___eval_debug_assertions(Vexample___024root* vlSelf) {
     if (false && vlSelf) {}  // Prevent unused
     Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_debug_assertions\n"); );
+    // Body
+    if (VL_UNLIKELY((vlSelf->a & 0xfeU))) {
+        Verilated::overWidthError("a");}
+    if (VL_UNLIKELY((vlSelf->b & 0xfeU))) {
+        Verilated::overWidthError("b");}
 }
 #endif  // VL_DEBUG

npc/obj/Vexample___024root__DepSet_hcb5acca5__0__Slow.cpp

@@ -11,23 +11,10 @@ VL_ATTR_COLD void Vexample___024root___eval_static(Vexample___024root* vlSelf) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_static\n"); );
 }
 
-VL_ATTR_COLD void Vexample___024root___eval_initial__TOP(Vexample___024root* vlSelf);
-
 VL_ATTR_COLD void Vexample___024root___eval_initial(Vexample___024root* vlSelf) {
     if (false && vlSelf) {}  // Prevent unused
     Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_initial\n"); );
-    // Body
-    Vexample___024root___eval_initial__TOP(vlSelf);
-}
-
-VL_ATTR_COLD void Vexample___024root___eval_initial__TOP(Vexample___024root* vlSelf) {
-    if (false && vlSelf) {}  // Prevent unused
-    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_initial__TOP\n"); );
-    // Body
-    VL_WRITEF("Hello World\n");
-    VL_FINISH_MT("vsrc/example.v", 2, "");
 }
 
 VL_ATTR_COLD void Vexample___024root___eval_final(Vexample___024root* vlSelf) {
@@ -36,12 +23,97 @@ VL_ATTR_COLD void Vexample___024root___eval_final(Vexample___024root* vlSelf) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_final\n"); );
 }
 
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vexample___024root___dump_triggers__stl(Vexample___024root* vlSelf);
+#endif  // VL_DEBUG
+VL_ATTR_COLD bool Vexample___024root___eval_phase__stl(Vexample___024root* vlSelf);
+
 VL_ATTR_COLD void Vexample___024root___eval_settle(Vexample___024root* vlSelf) {
     if (false && vlSelf) {}  // Prevent unused
     Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_settle\n"); );
+    // Init
+    IData/*31:0*/ __VstlIterCount;
+    CData/*0:0*/ __VstlContinue;
+    // Body
+    __VstlIterCount = 0U;
+    vlSelf->__VstlFirstIteration = 1U;
+    __VstlContinue = 1U;
+    while (__VstlContinue) {
+        if (VL_UNLIKELY((0x64U < __VstlIterCount))) {
+#ifdef VL_DEBUG
+            Vexample___024root___dump_triggers__stl(vlSelf);
+#endif
+            VL_FATAL_MT("vsrc/example.v", 1, "", "Settle region did not converge.");
+        }
+        __VstlIterCount = ((IData)(1U) + __VstlIterCount);
+        __VstlContinue = 0U;
+        if (Vexample___024root___eval_phase__stl(vlSelf)) {
+            __VstlContinue = 1U;
+        }
+        vlSelf->__VstlFirstIteration = 0U;
+    }
 }
 
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vexample___024root___dump_triggers__stl(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___dump_triggers__stl\n"); );
+    // Body
+    if ((1U & (~ (IData)(vlSelf->__VstlTriggered.any())))) {
+        VL_DBG_MSGF("         No triggers active\n");
+    }
+    if ((1ULL & vlSelf->__VstlTriggered.word(0U))) {
+        VL_DBG_MSGF("         'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n");
+    }
+}
+#endif  // VL_DEBUG
+
+void Vexample___024root___ico_sequent__TOP__0(Vexample___024root* vlSelf);
+
+VL_ATTR_COLD void Vexample___024root___eval_stl(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_stl\n"); );
+    // Body
+    if ((1ULL & vlSelf->__VstlTriggered.word(0U))) {
+        Vexample___024root___ico_sequent__TOP__0(vlSelf);
+    }
+}
+
+VL_ATTR_COLD void Vexample___024root___eval_triggers__stl(Vexample___024root* vlSelf);
+
+VL_ATTR_COLD bool Vexample___024root___eval_phase__stl(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___eval_phase__stl\n"); );
+    // Init
+    CData/*0:0*/ __VstlExecute;
+    // Body
+    Vexample___024root___eval_triggers__stl(vlSelf);
+    __VstlExecute = vlSelf->__VstlTriggered.any();
+    if (__VstlExecute) {
+        Vexample___024root___eval_stl(vlSelf);
+    }
+    return (__VstlExecute);
+}
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vexample___024root___dump_triggers__ico(Vexample___024root* vlSelf) {
+    if (false && vlSelf) {}  // Prevent unused
+    Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___dump_triggers__ico\n"); );
+    // Body
+    if ((1U & (~ (IData)(vlSelf->__VicoTriggered.any())))) {
+        VL_DBG_MSGF("         No triggers active\n");
+    }
+    if ((1ULL & vlSelf->__VicoTriggered.word(0U))) {
+        VL_DBG_MSGF("         'ico' region trigger index 0 is active: Internal 'ico' trigger - first iteration\n");
+    }
+}
+#endif  // VL_DEBUG
+
 #ifdef VL_DEBUG
 VL_ATTR_COLD void Vexample___024root___dump_triggers__act(Vexample___024root* vlSelf) {
     if (false && vlSelf) {}  // Prevent unused
@@ -70,4 +142,8 @@ VL_ATTR_COLD void Vexample___024root___ctor_var_reset(Vexample___024root* vlSelf
     if (false && vlSelf) {}  // Prevent unused
     Vexample__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
     VL_DEBUG_IF(VL_DBG_MSGF("+    Vexample___024root___ctor_var_reset\n"); );
+    // Body
+    vlSelf->a = VL_RAND_RESET_I(1);
+    vlSelf->b = VL_RAND_RESET_I(1);
+    vlSelf->f = VL_RAND_RESET_I(1);
 }

npc/obj/Vexample_classes.mk

@@ -30,6 +30,7 @@ VM_CLASSES_FAST += \
 # Generated module classes, non-fast-path, compile with low/medium optimization
 VM_CLASSES_SLOW += \
 	Vexample___024root__Slow \
+	Vexample___024root__DepSet_h625e39dc__0__Slow \
 	Vexample___024root__DepSet_hcb5acca5__0__Slow \
 
 # Generated support classes, fast-path, compile with highest optimization

npc/vsrc/example.v

@@ -1,3 +1,7 @@
-module our;
+module top(
-     initial begin $display("Hello World"); $finish; end
+  input a,
+  input b,
+  output f
+);
+  assign f = a ^ b;
 endmodule