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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 18:28:18  up  21:26,  2 users,  load average: 1.13, 0.58, 0.53
This commit is contained in:
tracer-ysyx 2023-12-23 18:28:18 +08:00 committed by xinyangli
parent a3aa285f55
commit b66f0c6d56
2 changed files with 15 additions and 7 deletions
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14
npc/Makefile
View file

@ -1,24 +1,24 @@
VERILATOR := verilator
VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(wildcard csrc/*.cpp)
PREFIX ?= ./build
PREFIX ?= .
OBJDIR := $(PREFIX)/obj
all: $(OBJDIR)
$(MAKE) -C $(OBJDIR) -f Vexample.mk
$(MAKE) -j -C $(OBJDIR) -f Vexample.mk Vexample
sim: $(OBJDIR)
sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Write this Makefile by your self."
$(OBJDIR)/Vexample
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
$(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $(OBJDIR)
verilator --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile
.phony: clean
.PHONY: clean
clean:
$(RM) -r $(OBJDIR)

8
npc/obj/Vexample__ALL.cpp Normal file
View file

@ -0,0 +1,8 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vexample.cpp"
#include "Vexample___024root__DepSet_h625e39dc__0.cpp"
#include "Vexample___024root__DepSet_hcb5acca5__0.cpp"
#include "Vexample___024root__Slow.cpp"
#include "Vexample___024root__DepSet_hcb5acca5__0__Slow.cpp"
#include "Vexample__Syms.cpp"