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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  09:35:05  up   0:25,  2 users,  load average: 1.25, 1.08, 0.87
This commit is contained in:
tracer-ysyx 2024-03-09 09:35:05 +08:00 committed by xinyangli
parent dee37632f1
commit c97e7271b7
2 changed files with 1 additions and 20 deletions
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10
npc/core/src/main/scala/Main.scala
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@ -2,10 +2,8 @@ package npc
import chisel3._ import chisel3._
import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse} import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
import chisel3.util.{SRAM}
import chisel3.stage.ChiselOption import chisel3.stage.ChiselOption
import npc.util.{ KeyboardSegController, RegisterFile } import npc.util.KeyboardSegController
import flowpc.components.ProgramCounter
class Switch extends Module { class Switch extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
@ -33,9 +31,3 @@ class Keyboard extends Module {
io.segs := seg_handler.io.segs io.segs := seg_handler.io.segs
} }
class Flowpc extends Module {
val io = IO(new Bundle { })
val register_file = new RegisterFile(readPorts = 2);
val pc = new ProgramCounter(32);
val adder = new SRAM()
}

11
npc/core/src/main/scala/ProgramCounter.scala
View file

@ -1,11 +0,0 @@
package flowpc.components
import chisel3._
import chisel3.util.{Valid}
class ProgramCounter (width: Int) extends Module {
val io = new Bundle {
val next_pc = Input(Flipped(Valid(UInt(width.W))))
val pc = Output(UInt(width.W))
}
io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc)
}