From c97e7271b7423f971d957a63eb5cac3e0d5aa1d4 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Sat, 9 Mar 2024 09:35:05 +0800 Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?= =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.6.19=20#1-?= =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:11?= =?UTF-8?q?=20UTC=202024=20x86=5F64=20GNU/Linux=20=20=2009:35:05=20=20up?= =?UTF-8?q?=20=20=200:25,=20=202=20users,=20=20load=20average:=201.25,=201?= =?UTF-8?q?.08,=200.87?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/Main.scala | 10 +--------- npc/core/src/main/scala/ProgramCounter.scala | 11 ----------- 2 files changed, 1 insertion(+), 20 deletions(-) delete mode 100644 npc/core/src/main/scala/ProgramCounter.scala diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index bf1ffab..c06bc8e 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -2,10 +2,8 @@ package npc import chisel3._ import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse} -import chisel3.util.{SRAM} import chisel3.stage.ChiselOption -import npc.util.{ KeyboardSegController, RegisterFile } -import flowpc.components.ProgramCounter +import npc.util.KeyboardSegController class Switch extends Module { val io = IO(new Bundle { @@ -33,9 +31,3 @@ class Keyboard extends Module { io.segs := seg_handler.io.segs } -class Flowpc extends Module { - val io = IO(new Bundle { }) - val register_file = new RegisterFile(readPorts = 2); - val pc = new ProgramCounter(32); - val adder = new SRAM() -} diff --git a/npc/core/src/main/scala/ProgramCounter.scala b/npc/core/src/main/scala/ProgramCounter.scala deleted file mode 100644 index 0687f9a..0000000 --- a/npc/core/src/main/scala/ProgramCounter.scala +++ /dev/null @@ -1,11 +0,0 @@ -package flowpc.components -import chisel3._ -import chisel3.util.{Valid} - -class ProgramCounter (width: Int) extends Module { - val io = new Bundle { - val next_pc = Input(Flipped(Valid(UInt(width.W)))) - val pc = Output(UInt(width.W)) - } - io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc) -}