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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 19:41:35  up  22:39,  2 users,  load average: 0.53, 0.50, 0.54
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tracer-ysyx 2023-12-23 19:41:35 +08:00 committed by xinyangli
parent 8303b1d6fe
commit a58f8d9020
1 changed files with 2 additions and 1 deletions
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3
npc/Makefile
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@ -8,7 +8,8 @@ all: $(OBJDIR)
sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
$(OBJDIR)/Vexample