ysyx-workbench/npc/Makefile
tracer-ysyx a58f8d9020 > sim RTL
ysyx_22040000 李心杨
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2023-12-23 19:41:35 +08:00

25 lines
544 B
Makefile

VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
PREFIX ?= build
OBJDIR := $(PREFIX)/obj
all: $(OBJDIR)
$(MAKE) -j -C $(OBJDIR) -f Vexample.mk Vexample
sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
$(OBJDIR)/Vexample
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
verilator --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile
.PHONY: clean
clean:
$(RM) -r $(OBJDIR)