ysyx-workbench/npc/Makefile
tracer-ysyx b66f0c6d56 > sim RTL
ysyx_22040000 李心杨
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2023-12-23 18:28:18 +08:00

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Makefile

VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(wildcard csrc/*.cpp)
PREFIX ?= .
OBJDIR := $(PREFIX)/obj
all: $(OBJDIR)
$(MAKE) -j -C $(OBJDIR) -f Vexample.mk Vexample
sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Write this Makefile by your self."
$(OBJDIR)/Vexample
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
verilator --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile
.PHONY: clean
clean:
$(RM) -r $(OBJDIR)