ysyx-workbench/npc/Makefile
tracer-ysyx d6227bf009 > sim RTL
ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 17:33:03  up  20:31,  2 users,  load average: 1.50, 1.26, 0.99
2023-12-23 17:33:03 +08:00

19 lines
439 B
Makefile

VERILATOR := verilator
VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(wildcard csrc/*.cpp)
PREFIX ?= ./build
OBJDIR := $(PREFIX)/obj
all: $(OBJDIR)
$(MAKE) -C $(OBJDIR) -f Vexample.mk
sim: $(OBJDIR)
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Write this Makefile by your self."
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
$(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $(OBJDIR)
include ../Makefile