e3d600fc21
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 13:29:52 up 22:08, 2 users, load average: 1.26, 1.02, 1.00
6 lines
No EOL
87 B
Verilog
6 lines
No EOL
87 B
Verilog
module top(
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input [1:0] sw,
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output ledr
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);
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assign ledr = sw[1] ^ sw[0];
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endmodule |