> sim RTL

ysyx_22040000 李心杨
Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
 13:29:52  up  22:08,  2 users,  load average: 1.26, 1.02, 1.00

npc/Makefile

@@ -1,41 +1,60 @@
-VSRC := $(wildcard vsrc/*.v)
-CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
-CPPSRC += $(SRC_AUTO_BIND)
-NXDC_FILES = $(abspath constr/top.nxdc)
-
+NVBOARD_HOME ?= $(abspath ../nvboard)
 PREFIX ?= build
 OBJDIR := $(PREFIX)/obj
+
+VSRC := $(wildcard vsrc/*.v)
+SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
+CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
+# TODO: fix this ugly way to find nvboard.a
+CPPSRCS += $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
+NXDC_FILES = $(abspath constr/top.nxdc)
 SUBMAKE := $(OBJDIR)/Vexample.mk
+
 VERILATOR_FLAGS := --cc --exe
-NVBOARD_HOME ?= $(abspath ../nvboard)
+CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
+LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
 
-all: sim $(SRC_AUTO_BIND)
+all: sim nvboard
 
-sim: VERILATOR_FLAGS += --trace
-sim: $(VSRC) $(CPPSRC) $(OBJDIR)/Vexample
-	$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
+sim: VERILATOR_FLAGS += --trace 
+sim: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample git_trace
 	@echo "Running" $(OBJDIR)/Vexample "..."
 	@echo "================================"
 	@$(OBJDIR)/Vexample
+
+nvboard: OBJDIR := $(PREFIX)/nvobj
+nvboard: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
+nvboard: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample
+	@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample
+
 	
 $(OBJDIR)/Vexample: $(SUBMAKE)
 	$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
 	
-$(SUBMAKE): $(VSRC) $(CPPSRC) $(OBJDIR)
-	verilator $(VERILATOR_FLAGS) \
-		--Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRC)
-# $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) \ 
+$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR)
+	verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS)
 
 $(OBJDIR):
 	mkdir -p $(OBJDIR)
 
-SRC_AUTO_BIND = $(abspath $(PREFIX)/auto_bind.cpp)
-$(SRC_AUTO_BIND): $(NXDC_FILES)
-	python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $^ $@
+$(SRC_AUTO_BIND): $(NXDC_FILES) $(OBJDIR)
+	NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
 
+
+ifneq (,$(wildcard ../Makefile))
 include ../Makefile
+endif
+
+ifeq (,$(wildcard ../Makefile))
+define git_commit
+endef
+endif
+
+git_trace: 
+	$(call git_commit, "sim RTL")
+
 
 .PHONY: clean 
 
 clean: 
-	$(RM) -r $(OBJDIR)
+	$(RM) -r $(PREFIX)

npc/csrc/main.cpp

@@ -3,9 +3,12 @@
 #include <cstdlib>
 #include <verilated.h>
 #include <verilated_vcd_c.h>
-#include "Vexample.h"
+#include <Vexample.h>
+#include <nvboard.h>
 
-#define MAX_SIM_TIME 100
+const int MAX_SIM_TIME=100;
+
+void nvboard_bind_all_pins(Vexample* top);
 
 int main(int argc, char **argv, char **env) {
     int sim_time = 0;
@@ -14,19 +17,27 @@ int main(int argc, char **argv, char **env) {
 
     Verilated::traceEverOn(true);
     VerilatedVcdC *m_trace = new VerilatedVcdC; 
+    nvboard_bind_all_pins(top);
+    nvboard_init();
+#ifdef VERILATOR_TRACE
     top->trace(m_trace, 5);
     m_trace->open("waveform.vcd");
-    for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
-        int a = rand() & 1;
-        int b = rand() & 1;
-        top->a = a;
-        top->b = b;
+#endif
+    // for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
+    while (true) {
+        nvboard_update();
+        // CData sw = rand() & 0b11;
+        // top->sw = sw;
         top->eval();
-        printf("a = %d, b = %d, f = %d\n", a, b, top->f);
-        assert(top->f == (a ^ b));
+        // printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
+        // assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
+#ifdef VERILATOR_TRACE
         m_trace->dump(sim_time);
+#endif
     }
+#ifdef VERILATOR_TRACE
     m_trace->close();
+#endif
     delete top;
     exit(EXIT_SUCCESS);
 }

npc/csrc_nvboard/main.cpp

@@ -0,0 +1,23 @@
+#include <cstdlib>
+#include <cassert>
+#include <cstdlib>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include <Vexample.h>
+#include <nvboard.h>
+
+const int MAX_SIM_TIME=100;
+
+void nvboard_bind_all_pins(Vexample* top);
+
+int main(int argc, char **argv, char **env) {
+    Vexample *top = new Vexample;
+
+    nvboard_bind_all_pins(top);
+    nvboard_init();
+    while (true) {
+        nvboard_update();
+        top->eval();
+    }
+    delete top;
+}

npc/flake.nix

@@ -13,12 +13,15 @@
             verilator
             gtkwave
             gcc
+            gdb
             bear
             clang-tools
             rnix-lsp
           ];
 
           nativeBuildInputs = with pkgs; [
+            SDL2
+            SDL2_image
             python3
           ];
 

npc/vsrc/example.v

@@ -1,7 +1,6 @@
 module top(
-  input a,
-  input b,
-  output f
+  input [1:0] sw,
+  output ledr
 );
-  assign f = a ^ b;
+  assign ledr = sw[1] ^ sw[0];
 endmodule