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> nvboard

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ysyx_22040000 李心杨
Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
 17:24:30  up   2:11,  2 users,  load average: 1.06, 1.29, 1.11
This commit is contained in:
tracer-ysyx 2024-01-04 17:24:30 +08:00 committed by xinyangli
parent 8dfae1f22d
commit fb03cbe36a
1 changed files with 15 additions and 13 deletions
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28
npc/Makefile
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@ -23,6 +23,19 @@ endef
all: sim-bin nvboard-bin all: sim-bin nvboard-bin
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc)
$(SRC_AUTO_BIND): $(NXDC_FILES)
NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
nvboard-bin: OBJDIR := $(PREFIX)/nvobj
nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# TODO: fix this awkward way to find nvboard.a
nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
$(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE) $(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
@$(call colorize,"SUBMAKE",$^) @$(call colorize,"SUBMAKE",$^)
$(MAKE) -s -C $(OBJDIR) -f $(notdir $(SUBMAKE)) V$(CHISEL_TOP_MODULE) $(MAKE) -s -C $(OBJDIR) -f $(notdir $(SUBMAKE)) V$(CHISEL_TOP_MODULE)
@ -38,11 +51,6 @@ $(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
@$(call colorize,"CIRCT",$^) @$(call colorize,"CIRCT",$^)
sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)" sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)"
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc)
$(SRC_AUTO_BIND): $(NXDC_FILES)
NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
compile_commands.json: clean compile_commands.json: clean
$(MAKE) $(CHISEL_VDIR)/filelist.f $(MAKE) $(CHISEL_VDIR)/filelist.f
$(RM) compile_commands.json $(RM) compile_commands.json
@ -54,14 +62,6 @@ compile_commands.json: clean
sim-bin: VERILATOR_FLAGS += --trace sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE) sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
nvboard-bin: OBJDIR := $(PREFIX)/nvobj
nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# TODO: fix this awkward way to find nvboard.a
nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
chisel-src: $(CHISEL_VDIR)/filelist.f chisel-src: $(CHISEL_VDIR)/filelist.f
$(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv)) $(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv))
@echo "GENERATED: $(CHISEL_VSRC)" @echo "GENERATED: $(CHISEL_VSRC)"
@ -81,6 +81,8 @@ git_trace_nvboard:
nvboard: OBJDIR := $(PREFIX)/nvobj nvboard: OBJDIR := $(PREFIX)/nvobj
nvboard: nvboard-bin git_trace_nvboard nvboard: nvboard-bin git_trace_nvboard
@echo "Running NVBoard ..."
@echo "================================"
@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE) @NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
sim: sim-bin git_trace_sim sim: sim-bin git_trace_sim