diff --git a/npc/Makefile b/npc/Makefile
index dae477a..5e9d595 100644
--- a/npc/Makefile
+++ b/npc/Makefile
@@ -22,6 +22,19 @@ define colorize
 endef
 
 all: sim-bin nvboard-bin
+
+SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
+NXDC_FILES := $(abspath constr/top.nxdc)
+$(SRC_AUTO_BIND): $(NXDC_FILES)
+	NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
+
+nvboard-bin: OBJDIR := $(PREFIX)/nvobj
+nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
+# TODO: fix this awkward way to find nvboard.a
+nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
+nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
+
+nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
 	
 $(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
 	@$(call colorize,"SUBMAKE",$^)
@@ -38,11 +51,6 @@ $(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
 	@$(call colorize,"CIRCT",$^)
 	sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)"
 
-SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
-NXDC_FILES := $(abspath constr/top.nxdc)
-$(SRC_AUTO_BIND): $(NXDC_FILES)
-	NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
-
 compile_commands.json: clean
 	$(MAKE) $(CHISEL_VDIR)/filelist.f
 	$(RM) compile_commands.json
@@ -54,14 +62,6 @@ compile_commands.json: clean
 sim-bin: VERILATOR_FLAGS += --trace 
 sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
 
-nvboard-bin: OBJDIR := $(PREFIX)/nvobj
-nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
-# TODO: fix this awkward way to find nvboard.a
-nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
-nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
-
-nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
-
 chisel-src: $(CHISEL_VDIR)/filelist.f
 	$(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv))
 	@echo "GENERATED: $(CHISEL_VSRC)"
@@ -81,6 +81,8 @@ git_trace_nvboard:
 
 nvboard: OBJDIR := $(PREFIX)/nvobj
 nvboard: nvboard-bin git_trace_nvboard
+	@echo "Running NVBoard ..."
+	@echo "================================"
 	@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
 
 sim: sim-bin git_trace_sim