> sim RTL

ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 17:28:21  up  20:26,  2 users,  load average: 1.06, 0.86, 0.79
This commit is contained in:
tracer-ysyx 2023-12-23 17:28:21 +08:00 committed by xinyangli
parent 0c20423285
commit f46c08ec71
2 changed files with 1 additions and 9 deletions

View file

@ -11,6 +11,6 @@ sim: obj_dir
@echo "Write this Makefile by your self."
obj_dir: $(VSRC) $(CPPSRC)
$(VERILATOR) $(VSRC:%=--cc %) $< $(CPPSRC:%=--exe %) --Mdir $@
$(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $@
include ../Makefile

View file

@ -1,8 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vexample.cpp"
#include "Vexample___024root__DepSet_h625e39dc__0.cpp"
#include "Vexample___024root__DepSet_hcb5acca5__0.cpp"
#include "Vexample___024root__Slow.cpp"
#include "Vexample___024root__DepSet_hcb5acca5__0__Slow.cpp"
#include "Vexample__Syms.cpp"