ysyx-workbench/npc/Makefile
tracer-ysyx f46c08ec71 > sim RTL
ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 17:28:21  up  20:26,  2 users,  load average: 1.06, 0.86, 0.79
2023-12-23 17:28:21 +08:00

16 lines
362 B
Makefile

VERILATOR := verilator
VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(wildcard csrc/*.cpp)
all:
@echo "Write this Makefile by your self."
sim: obj_dir
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Write this Makefile by your self."
obj_dir: $(VSRC) $(CPPSRC)
$(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $@
include ../Makefile