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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  15:23:35  up 3 days  6:14,  2 users,  load average: 1.57, 1.47, 1.51
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tracer-ysyx 2024-03-12 15:23:35 +08:00 committed by xinyangli
parent a7d59b4d37
commit dd809b6712
1 changed files with 10 additions and 3 deletions
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13
npc/core/src/main/scala/Main.scala
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@ -83,15 +83,17 @@ class Flow extends Module {
ram.readPorts(0).address := pc.out ram.readPorts(0).address := pc.out
val inst = ram.readPorts(0).data val inst = ram.readPorts(0).data
import control.pc.SrcSelect._
pc.in.pcSrcs(pStaticNpc.litValue.toInt) := pc.out + 4.U
pc.in.pcSrcs(pBranchResult.litValue.toInt) := alu.out.result
control.inst := inst control.inst := inst
reg.control <> control.reg reg.control <> control.reg
pc.control <> control.pc pc.control <> control.pc
alu.control <> control.alu alu.control <> control.alu
import control.reg.WriteSelect._ import control.reg.WriteSelect._
import control.pc.SrcSelect._
import control.alu.OpSelect._
reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result
// TODO: Read address in load command goes here // TODO: Read address in load command goes here
ram.readPorts(1).enable := false.B ram.readPorts(1).enable := false.B
@ -101,6 +103,11 @@ class Flow extends Module {
reg.in.rs(0) := inst(19, 15) reg.in.rs(0) := inst(19, 15)
reg.in.rs(1) := inst(24, 20) reg.in.rs(1) := inst(24, 20)
// TODO: Memory write goes here
ram.writePorts(0).address := 1.U
ram.writePorts(0).data := 1.U
ram.writePorts(0).enable := false.B
alu.in.a := reg.out.src(0) alu.in.a := reg.out.src(0)
alu.in.b := reg.out.src(1) alu.in.b := reg.out.src(1)
} }