From dd809b6712800b8b725e3dd946df7613dfd6fe2e Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Tue, 12 Mar 2024 15:23:35 +0800 Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?= =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.6.19=20#1-?= =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:11?= =?UTF-8?q?=20UTC=202024=20x86=5F64=20GNU/Linux=20=20=2015:23:35=20=20up?= =?UTF-8?q?=203=20days=20=206:14,=20=202=20users,=20=20load=20average:=201?= =?UTF-8?q?.57,=201.47,=201.51?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/Main.scala | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index 0dc0c8d..0a21ab7 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -83,15 +83,17 @@ class Flow extends Module { ram.readPorts(0).address := pc.out val inst = ram.readPorts(0).data + import control.pc.SrcSelect._ + + pc.in.pcSrcs(pStaticNpc.litValue.toInt) := pc.out + 4.U + pc.in.pcSrcs(pBranchResult.litValue.toInt) := alu.out.result + control.inst := inst reg.control <> control.reg pc.control <> control.pc alu.control <> control.alu import control.reg.WriteSelect._ - import control.pc.SrcSelect._ - import control.alu.OpSelect._ - reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result // TODO: Read address in load command goes here ram.readPorts(1).enable := false.B @@ -101,6 +103,11 @@ class Flow extends Module { reg.in.rs(0) := inst(19, 15) reg.in.rs(1) := inst(24, 20) + // TODO: Memory write goes here + ram.writePorts(0).address := 1.U + ram.writePorts(0).data := 1.U + ram.writePorts(0).enable := false.B + alu.in.a := reg.out.src(0) alu.in.b := reg.out.src(1) }