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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 17:33:03  up  20:31,  2 users,  load average: 1.50, 1.26, 0.99
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tracer-ysyx 2023-12-23 17:33:03 +08:00 committed by xinyangli
parent a315f9ac2b
commit d6227bf009
1 changed files with 6 additions and 5 deletions
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11
npc/Makefile
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@ -2,17 +2,18 @@ VERILATOR := verilator
VSRC := $(wildcard vsrc/*.v) VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(wildcard csrc/*.cpp) CPPSRC := $(wildcard csrc/*.cpp)
PREFIX ?= . PREFIX ?= ./build
OBJDIR := $(PREFIX)/obj OBJDIR := $(PREFIX)/obj
all: all: $(OBJDIR)
@echo "Write this Makefile by your self." $(MAKE) -C $(OBJDIR) -f Vexample.mk
sim: obj_dir sim: $(OBJDIR)
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!! $(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Write this Makefile by your self." @echo "Write this Makefile by your self."
obj_dir: $(VSRC) $(CPPSRC) $(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
$(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $(OBJDIR) $(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $(OBJDIR)
include ../Makefile include ../Makefile