> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 20:47:01 up 2 days 19:47, 2 users, load average: 0.93, 0.76, 0.85
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5 changed files with 21 additions and 14 deletions
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@ -1,3 +1,5 @@
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package npc.util
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import chisel3._
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import chisel3._
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class RegisterFile(readPorts: Int) extends Module {
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class RegisterFile(readPorts: Int) extends Module {
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@ -32,21 +32,28 @@ class SegGenerator(seg_count: Int) extends Module {
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0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
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0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
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).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
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).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
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// val keycode = Mux(io.keycode.ready && io.keycode.valid, io.keycode.bits, keycode)
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val keycode = RegInit(0.U(8.W))
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val keycode = RegEnable(io.keycode.bits, io.keycode.ready && io.keycode.valid)
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val counter = Counter(0xFF)
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val release_state = false.B
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when(io.keycode.ready && io.keycode.valid) {
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when(io.keycode.bits === 0xF0.U) {
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release_state := true.B
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}.elsewhen(!release_state) {
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keycode := io.keycode.bits
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counter.inc()
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}
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}
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val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
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val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
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val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
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val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
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val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
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val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
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val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val (counter, _) = Counter(io.keycode.valid && io.keycode.ready && io.keycode.bits =/= keycode, 0xFF)
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val count_digits = VecInit(counter(3,0)) ++ VecInit(counter(7,4))
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val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val count_digits = VecInit(counter.value(3,0)) ++ VecInit(counter.value(7,4))
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val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
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seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
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io.segs := seg_regs
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io.segs := seg_regs
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}
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}
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@ -5,6 +5,8 @@ import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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import chiseltest.simulator.WriteVcdAnnotation
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import npc.util._
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class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
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class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
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def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
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def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
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require(keycode >= 0 && keycode < 0xFF)
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require(keycode >= 0 && keycode < 0xFF)
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@ -57,11 +59,6 @@ class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
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})
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})
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}
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}
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}
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}
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import npc.Keyboard
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"Keyboard Simulation" in {
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test(new Keyboard) { c =>
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}
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}
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}
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}
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class SegSpec extends AnyFreeSpec with ChiselScalatestTester {
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class SegSpec extends AnyFreeSpec with ChiselScalatestTester {
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@ -5,6 +5,8 @@ import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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import chiseltest.simulator.WriteVcdAnnotation
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import npc.util._
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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"with 2 read ports" in {
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@ -14,7 +14,6 @@
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#undef CLASS_SYSTEM_HEADER_NAME
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#undef CLASS_SYSTEM_HEADER_NAME
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#undef CLASS_SYSTEM_HEADER_NAME_IMPL
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#undef CLASS_SYSTEM_HEADER_NAME_IMPL
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const int MAX_SIM_TIME = 100;
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int keycode = 0;
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int keycode = 0;
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template <class F> void cycle(VERILATOR_TOPMODULE *top, F &&f) {
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template <class F> void cycle(VERILATOR_TOPMODULE *top, F &&f) {
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