diff --git a/npc/core/src/main/scala/RegisterFile.scala b/npc/core/src/main/scala/RegisterFile.scala
index 3f1d50c..fbf8a94 100644
--- a/npc/core/src/main/scala/RegisterFile.scala
+++ b/npc/core/src/main/scala/RegisterFile.scala
@@ -1,3 +1,5 @@
+package npc.util
+
 import chisel3._
 
 class RegisterFile(readPorts: Int) extends Module {
diff --git a/npc/core/src/main/scala/SegGenerator.scala b/npc/core/src/main/scala/SegGenerator.scala
index 0b4ac55..574cd95 100644
--- a/npc/core/src/main/scala/SegGenerator.scala
+++ b/npc/core/src/main/scala/SegGenerator.scala
@@ -32,21 +32,28 @@ class SegGenerator(seg_count: Int) extends Module {
     0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
   ).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
 
-  // val keycode = Mux(io.keycode.ready && io.keycode.valid, io.keycode.bits, keycode)
-  val keycode = RegEnable(io.keycode.bits, io.keycode.ready && io.keycode.valid)
+  val keycode = RegInit(0.U(8.W))
+  val counter = Counter(0xFF)
+  val release_state = false.B
+  when(io.keycode.ready && io.keycode.valid) {
+    when(io.keycode.bits === 0xF0.U) {
+      release_state := true.B
+    }.elsewhen(!release_state) {
+      keycode := io.keycode.bits
+      counter.inc()
+    }
+  }
+
   val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
   val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
+
   val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
   val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
   val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
-  val (counter, _) = Counter(io.keycode.valid && io.keycode.ready && io.keycode.bits =/= keycode, 0xFF)
-  val count_digits = VecInit(counter(3,0)) ++ VecInit(counter(7,4))
-  val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
 
+  val count_digits = VecInit(counter.value(3,0)) ++ VecInit(counter.value(7,4))
+  val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
   seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
 
   io.segs := seg_regs
 }
-
-
-
diff --git a/npc/core/src/test/scala/Keyboard.scala b/npc/core/src/test/scala/Keyboard.scala
index 3f22b84..24723cc 100644
--- a/npc/core/src/test/scala/Keyboard.scala
+++ b/npc/core/src/test/scala/Keyboard.scala
@@ -5,6 +5,8 @@ import chiseltest._
 import org.scalatest.freespec.AnyFreeSpec
 import chiseltest.simulator.WriteVcdAnnotation
 
+import npc.util._
+
 class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
   def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
     require(keycode >= 0 && keycode < 0xFF)
@@ -57,11 +59,6 @@ class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
       })
     }
   }
-  import npc.Keyboard
-  "Keyboard Simulation" in {
-    test(new Keyboard) { c => 
-    }
-  }
 }
 
 class SegSpec extends AnyFreeSpec with ChiselScalatestTester {
diff --git a/npc/core/src/test/scala/Main.scala b/npc/core/src/test/scala/Main.scala
index 03c00d3..c9c093e 100644
--- a/npc/core/src/test/scala/Main.scala
+++ b/npc/core/src/test/scala/Main.scala
@@ -5,6 +5,8 @@ import chiseltest._
 import org.scalatest.freespec.AnyFreeSpec
 import chiseltest.simulator.WriteVcdAnnotation
 
+import npc.util._
+
 class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
   "RegisterFile should work" - {
     "with 2 read ports" in {
diff --git a/npc/csrc_nvboard/Keyboard/main.cpp b/npc/csrc_nvboard/Keyboard/main.cpp
index 0218bd1..8f5ea74 100644
--- a/npc/csrc_nvboard/Keyboard/main.cpp
+++ b/npc/csrc_nvboard/Keyboard/main.cpp
@@ -14,7 +14,6 @@
 #undef CLASS_SYSTEM_HEADER_NAME
 #undef CLASS_SYSTEM_HEADER_NAME_IMPL
 
-const int MAX_SIM_TIME = 100;
 int keycode = 0;
 
 template <class F> void cycle(VERILATOR_TOPMODULE *top, F &&f) {