> configure(npc)

ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  20:47:01  up 2 days 19:47,  2 users,  load average: 0.93, 0.76, 0.85
This commit is contained in:
tracer-ysyx 2024-01-10 20:47:01 +08:00 committed by xinyangli
parent d64383ffd0
commit d35f3cea17
5 changed files with 21 additions and 14 deletions

View file

@ -1,3 +1,5 @@
package npc.util
import chisel3._
class RegisterFile(readPorts: Int) extends Module {

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@ -32,21 +32,28 @@ class SegGenerator(seg_count: Int) extends Module {
0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
// val keycode = Mux(io.keycode.ready && io.keycode.valid, io.keycode.bits, keycode)
val keycode = RegEnable(io.keycode.bits, io.keycode.ready && io.keycode.valid)
val keycode = RegInit(0.U(8.W))
val counter = Counter(0xFF)
val release_state = false.B
when(io.keycode.ready && io.keycode.valid) {
when(io.keycode.bits === 0xF0.U) {
release_state := true.B
}.elsewhen(!release_state) {
keycode := io.keycode.bits
counter.inc()
}
}
val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
val (counter, _) = Counter(io.keycode.valid && io.keycode.ready && io.keycode.bits =/= keycode, 0xFF)
val count_digits = VecInit(counter(3,0)) ++ VecInit(counter(7,4))
val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
val count_digits = VecInit(counter.value(3,0)) ++ VecInit(counter.value(7,4))
val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
io.segs := seg_regs
}

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@ -5,6 +5,8 @@ import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import npc.util._
class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
require(keycode >= 0 && keycode < 0xFF)
@ -57,11 +59,6 @@ class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
})
}
}
import npc.Keyboard
"Keyboard Simulation" in {
test(new Keyboard) { c =>
}
}
}
class SegSpec extends AnyFreeSpec with ChiselScalatestTester {

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@ -5,6 +5,8 @@ import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import npc.util._
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
"RegisterFile should work" - {
"with 2 read ports" in {

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@ -14,7 +14,6 @@
#undef CLASS_SYSTEM_HEADER_NAME
#undef CLASS_SYSTEM_HEADER_NAME_IMPL
const int MAX_SIM_TIME = 100;
int keycode = 0;
template <class F> void cycle(VERILATOR_TOPMODULE *top, F &&f) {