fix: missing files from git
This commit is contained in:
parent
77ea7e3b8c
commit
ccbcbabb27
5 changed files with 157 additions and 624 deletions
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.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.s
|
||||
|
||||
# target to generate assembly for a file
|
||||
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.cpp.s:
|
||||
$(MAKE) $(MAKESILENT) -f CMakeFiles/VMain.dir/build.make CMakeFiles/VMain.dir/nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.cpp.s
|
||||
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.cpp.s
|
||||
|
||||
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.o: nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.o
|
||||
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.o
|
||||
|
||||
# target to build an object file
|
||||
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.o:
|
||||
$(MAKE) $(MAKESILENT) -f CMakeFiles/VMain.dir/build.make CMakeFiles/VMain.dir/nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.o
|
||||
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.o
|
||||
|
||||
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.i: nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.i
|
||||
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.i
|
||||
|
||||
# target to preprocess a source file
|
||||
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.i:
|
||||
$(MAKE) $(MAKESILENT) -f CMakeFiles/VMain.dir/build.make CMakeFiles/VMain.dir/nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.i
|
||||
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.i
|
||||
|
||||
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.s: nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.s
|
||||
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.s
|
||||
|
||||
# target to generate assembly for a file
|
||||
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.s:
|
||||
$(MAKE) $(MAKESILENT) -f CMakeFiles/VMain.dir/build.make CMakeFiles/VMain.dir/nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.s
|
||||
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.s
|
||||
|
||||
# Help Target
|
||||
help:
|
||||
@echo "The following are some of the valid targets for this Makefile:"
|
||||
@echo "... all (the default if no target is provided)"
|
||||
@echo "... clean"
|
||||
@echo "... depend"
|
||||
@echo "... edit_cache"
|
||||
@echo "... install"
|
||||
@echo "... install/local"
|
||||
@echo "... install/strip"
|
||||
@echo "... list_install_components"
|
||||
@echo "... rebuild_cache"
|
||||
@echo "... ChiselBuild"
|
||||
@echo "... VMain"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Syms.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Syms.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Syms.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0__Slow.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0__Slow.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0__Slow.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_h3502859f__0.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_h3502859f__0.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_h3502859f__0.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_h3502859f__0__Slow.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_h3502859f__0__Slow.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_h3502859f__0__Slow.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_hda8ec1d0__0.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_hda8ec1d0__0.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_hda8ec1d0__0.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_hda8ec1d0__0__Slow.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_hda8ec1d0__0__Slow.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__DepSet_hda8ec1d0__0__Slow.s"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__Slow.o"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__Slow.i"
|
||||
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain___024root__Slow.s"
|
||||
@echo "... auto_bind.o"
|
||||
@echo "... auto_bind.i"
|
||||
@echo "... auto_bind.s"
|
||||
@echo "... csrc_nvboard/main.o"
|
||||
@echo "... csrc_nvboard/main.i"
|
||||
@echo "... csrc_nvboard/main.s"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated.o"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated.i"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated.s"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_cov.o"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_cov.i"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_cov.s"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.o"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.i"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.s"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.o"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.i"
|
||||
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.s"
|
||||
.PHONY : help
|
||||
|
||||
|
||||
|
||||
#=============================================================================
|
||||
# Special targets to cleanup operation of make.
|
||||
|
||||
# Special rule to run CMake to check the build system integrity.
|
||||
# No rule that depends on this can have commands that come from listfiles
|
||||
# because they might be regenerated.
|
||||
cmake_check_build_system:
|
||||
$(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0
|
||||
.PHONY : cmake_check_build_system
|
||||
|
||||
22
npc/core/build.sbt
Normal file
22
npc/core/build.sbt
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
ThisBuild / scalaVersion := "2.13.12"
|
||||
ThisBuild / version := "0.1.0"
|
||||
|
||||
|
||||
val chiselVersion = "5.1.0"
|
||||
|
||||
lazy val root = (project in file("."))
|
||||
.settings(
|
||||
name := "ChiselLearning",
|
||||
libraryDependencies ++= Seq(
|
||||
"org.chipsalliance" %% "chisel" % chiselVersion,
|
||||
"edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test"
|
||||
),
|
||||
scalacOptions ++= Seq(
|
||||
"-language:reflectiveCalls",
|
||||
"-deprecation",
|
||||
"-feature",
|
||||
"-Xcheckinit",
|
||||
"-Ymacro-annotations",
|
||||
),
|
||||
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
|
||||
)
|
||||
64
npc/core/src/main/scala/Reg.scala
Normal file
64
npc/core/src/main/scala/Reg.scala
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
package npc
|
||||
|
||||
import chisel3._
|
||||
import chisel3.stage.ChiselOption
|
||||
|
||||
class RegisterFile(readPorts: Int) extends Module {
|
||||
require(readPorts >= 0)
|
||||
val io = IO(new Bundle {
|
||||
val writeEnable = Input(Bool())
|
||||
val writeAddr = Input(UInt(5.W))
|
||||
val writeData = Input(UInt(32.W))
|
||||
val readAddr = Input(Vec(readPorts, UInt(5.W)))
|
||||
val readData = Output(Vec(readPorts, UInt(32.W)))
|
||||
})
|
||||
|
||||
val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
|
||||
for (i <- 1 until 32) {
|
||||
regFile(i) := regFile(i)
|
||||
}
|
||||
regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
|
||||
regFile(0) := 0.U
|
||||
|
||||
for (i <- 0 until readPorts) {
|
||||
io.readData(i) := regFile(io.readAddr(i))
|
||||
}
|
||||
}
|
||||
|
||||
class MuxGenerator(width: Int, nInput: Int) extends Module {
|
||||
require(width >= 0)
|
||||
require(nInput >= 1)
|
||||
require(nInput.toBinaryString.map(_ - '0').sum == 1)
|
||||
|
||||
val io = IO(new Bundle {
|
||||
val in = Input(Vec(nInput, UInt(width.W)))
|
||||
val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
|
||||
val out = Output(UInt(width.W))
|
||||
})
|
||||
|
||||
io.out := io.in(io.sel)
|
||||
}
|
||||
|
||||
class Test extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val in = Input(UInt(32.W))
|
||||
val out = Output(UInt(32.W))
|
||||
})
|
||||
|
||||
val regFile = Module(new RegisterFile(2))
|
||||
regFile.io.writeEnable := true.B
|
||||
regFile.io.writeAddr := 1.U
|
||||
regFile.io.writeData := io.in
|
||||
regFile.io.readAddr(0) := 0.U
|
||||
regFile.io.readAddr(1) := 1.U
|
||||
io.out := regFile.io.readData(1)
|
||||
}
|
||||
|
||||
class Switch extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val sw = Input(Vec(2, Bool()))
|
||||
val out = Output(Bool())
|
||||
})
|
||||
|
||||
io.out := io.sw(0) ^ io.sw(1)
|
||||
}
|
||||
71
npc/core/src/test/scala/Reg.scala
Normal file
71
npc/core/src/test/scala/Reg.scala
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
import chisel3._
|
||||
import chiseltest._
|
||||
import org.scalatest.freespec.AnyFreeSpec
|
||||
|
||||
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"RegisterFile should work" - {
|
||||
"with 2 read ports" in {
|
||||
test(new RegisterFile(2)) { c =>
|
||||
def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
|
||||
c.io.readAddr(port).poke(addr.U)
|
||||
c.io.readData(port).expect(value.U)
|
||||
}
|
||||
def write(addr: Int, value: Int): Unit = {
|
||||
c.io.writeEnable.poke(true.B)
|
||||
c.io.writeData.poke(value.U)
|
||||
c.io.writeAddr.poke(addr.U)
|
||||
c.clock.step(1)
|
||||
c.io.writeEnable.poke(false.B)
|
||||
}
|
||||
// everything should be 0 on init
|
||||
for (i <- 0 until 32) {
|
||||
readExpect(i, 0, port = 0)
|
||||
readExpect(i, 0, port = 1)
|
||||
}
|
||||
|
||||
// write 5 * addr + 3
|
||||
for (i <- 0 until 32) {
|
||||
write(i, 5 * i + 3)
|
||||
}
|
||||
|
||||
// check that the writes worked
|
||||
for (i <- 0 until 32) {
|
||||
readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class MuxGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"MuxGenerator should work" - {
|
||||
"when there are 2 inputs" in {
|
||||
test(new MuxGenerator(8, 2)) { c =>
|
||||
c.io.in(0).poke(0.U)
|
||||
c.io.in(1).poke(1.U)
|
||||
c.io.sel.poke(0.U)
|
||||
c.io.out.expect(0.U)
|
||||
c.io.sel.poke(1.U)
|
||||
c.io.out.expect(1.U)
|
||||
}
|
||||
}
|
||||
"when there are 1024 inputs" in {
|
||||
test(new MuxGenerator(32, 1024)) { c =>
|
||||
for (i <- 0 until 1024) {
|
||||
c.io.in(i).poke(i.U)
|
||||
}
|
||||
for (i <- 0 until 1024) {
|
||||
c.io.sel.poke(i.U)
|
||||
c.io.out.expect(i.U)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
"MuxGenerator should raise exception" - {
|
||||
"when nInput is not 2^n" in {
|
||||
assertThrows[IllegalArgumentException] {
|
||||
test(new MuxGenerator(8, 3)) { c => }
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue