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diff --git a/npc/core/build.sbt b/npc/core/build.sbt new file mode 100644 index 0000000..792a764 --- /dev/null +++ b/npc/core/build.sbt @@ -0,0 +1,22 @@ +ThisBuild / scalaVersion := "2.13.12" +ThisBuild / version := "0.1.0" + + +val chiselVersion = "5.1.0" + +lazy val root = (project in file(".")) + .settings( + name := "ChiselLearning", + libraryDependencies ++= Seq( + "org.chipsalliance" %% "chisel" % chiselVersion, + "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test" + ), + scalacOptions ++= Seq( + "-language:reflectiveCalls", + "-deprecation", + "-feature", + "-Xcheckinit", + "-Ymacro-annotations", + ), + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full), + ) \ No newline at end of file diff --git a/npc/core/src/main/scala/Reg.scala b/npc/core/src/main/scala/Reg.scala new file mode 100644 index 0000000..dd5dc4f --- /dev/null +++ b/npc/core/src/main/scala/Reg.scala @@ -0,0 +1,64 @@ +package npc + +import chisel3._ +import chisel3.stage.ChiselOption + +class RegisterFile(readPorts: Int) extends Module { + require(readPorts >= 0) + val io = IO(new Bundle { + val writeEnable = Input(Bool()) + val writeAddr = Input(UInt(5.W)) + val writeData = Input(UInt(32.W)) + val readAddr = Input(Vec(readPorts, UInt(5.W))) + val readData = Output(Vec(readPorts, UInt(32.W))) + }) + + val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W)))) + for (i <- 1 until 32) { + regFile(i) := regFile(i) + } + regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr)) + regFile(0) := 0.U + + for (i <- 0 until readPorts) { + io.readData(i) := regFile(io.readAddr(i)) + } +} + +class MuxGenerator(width: Int, nInput: Int) extends Module { + require(width >= 0) + require(nInput >= 1) + require(nInput.toBinaryString.map(_ - '0').sum == 1) + + val io = IO(new Bundle { + val in = Input(Vec(nInput, UInt(width.W))) + val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W)) + val out = Output(UInt(width.W)) + }) + + io.out := io.in(io.sel) +} + +class Test extends Module { + val io = IO(new Bundle { + val in = Input(UInt(32.W)) + val out = Output(UInt(32.W)) + }) + + val regFile = Module(new RegisterFile(2)) + regFile.io.writeEnable := true.B + regFile.io.writeAddr := 1.U + regFile.io.writeData := io.in + regFile.io.readAddr(0) := 0.U + regFile.io.readAddr(1) := 1.U + io.out := regFile.io.readData(1) +} + +class Switch extends Module { + val io = IO(new Bundle { + val sw = Input(Vec(2, Bool())) + val out = Output(Bool()) + }) + + io.out := io.sw(0) ^ io.sw(1) +} diff --git a/npc/core/src/test/scala/Reg.scala b/npc/core/src/test/scala/Reg.scala new file mode 100644 index 0000000..e287f48 --- /dev/null +++ b/npc/core/src/test/scala/Reg.scala @@ -0,0 +1,71 @@ +import chisel3._ +import chiseltest._ +import org.scalatest.freespec.AnyFreeSpec + +class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester { + "RegisterFile should work" - { + "with 2 read ports" in { + test(new RegisterFile(2)) { c => + def readExpect(addr: Int, value: Int, port: Int = 0): Unit = { + c.io.readAddr(port).poke(addr.U) + c.io.readData(port).expect(value.U) + } + def write(addr: Int, value: Int): Unit = { + c.io.writeEnable.poke(true.B) + c.io.writeData.poke(value.U) + c.io.writeAddr.poke(addr.U) + c.clock.step(1) + c.io.writeEnable.poke(false.B) + } + // everything should be 0 on init + for (i <- 0 until 32) { + readExpect(i, 0, port = 0) + readExpect(i, 0, port = 1) + } + + // write 5 * addr + 3 + for (i <- 0 until 32) { + write(i, 5 * i + 3) + } + + // check that the writes worked + for (i <- 0 until 32) { + readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2) + } + } + } + } +} + +class MuxGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester { + "MuxGenerator should work" - { + "when there are 2 inputs" in { + test(new MuxGenerator(8, 2)) { c => + c.io.in(0).poke(0.U) + c.io.in(1).poke(1.U) + c.io.sel.poke(0.U) + c.io.out.expect(0.U) + c.io.sel.poke(1.U) + c.io.out.expect(1.U) + } + } + "when there are 1024 inputs" in { + test(new MuxGenerator(32, 1024)) { c => + for (i <- 0 until 1024) { + c.io.in(i).poke(i.U) + } + for (i <- 0 until 1024) { + c.io.sel.poke(i.U) + c.io.out.expect(i.U) + } + } + } + } + "MuxGenerator should raise exception" - { + "when nInput is not 2^n" in { + assertThrows[IllegalArgumentException] { + test(new MuxGenerator(8, 3)) { c => } + } + } + } +}