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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  10:19:24  up 4 days  1:09,  2 users,  load average: 1.63, 1.47, 1.02
This commit is contained in:
tracer-ysyx 2024-03-13 10:19:24 +08:00 committed by xinyangli
parent aeed35376f
commit cb2ecd29ac
4 changed files with 11 additions and 6 deletions
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4
npc/core/anno.json Normal file
View file

@ -0,0 +1,4 @@
[{
"class": "firrtl.transforms.DontTouchAnnotation",
"target": "~Flow|Control"
}]

10
npc/core/src/main/scala/Main.scala
View file

@ -47,15 +47,13 @@ class Control(width: Int) extends Module {
val ControlMapping: Array[(BitPat, T)] = Array( val ControlMapping: Array[(BitPat, T)] = Array(
// Regs :: PC :: Exe // Regs :: PC :: Exe
// writeEnable :: writeSelect :: srcSelect :: // writeEnable :: writeSelect :: srcSelect ::
(addi, false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil), (addi, false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil),
// ("", false.B :: rAluOut :: pStaticNpc :: aOpNop :: HNil),
) )
def toBits(t: T): BitPat = { def toBits(t: T): BitPat = {
val list: List[Data] = t.toList val list: List[Data] = t.toList
list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduce(_ ## _) list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _)
} }
// val default = toBits(false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil).getWidth
val default = BitPat("b???????") val default = BitPat("b???????")
reg.writeEnable := false.B reg.writeEnable := false.B
@ -90,7 +88,7 @@ class Flow extends Module {
numReadPorts = 2, numReadPorts = 2,
numWritePorts = 1, numWritePorts = 1,
numReadwritePorts = 0, numReadwritePorts = 0,
// memoryFile = HexMemoryFile(memoryFile) memoryFile = HexMemoryFile("../resource/addi.txt")
) )
val control = Module(new Control(32)) val control = Module(new Control(32))
val reg = RegisterFile(32, dataType, 2, 2) val reg = RegisterFile(32, dataType, 2, 2)
@ -128,4 +126,6 @@ class Flow extends Module {
alu.in.a := reg.out.src(0) alu.in.a := reg.out.src(0)
alu.in.b := reg.out.src(1) alu.in.b := reg.out.src(1)
printf("Yes\n")
dontTouch(control.out)
} }

1
npc/core/src/main/scala/RegisterFile.scala
View file

@ -66,6 +66,7 @@ class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends
for (readPort <- readPorts) { for (readPort <- readPorts) {
readPort.data := regFile(readPort.addr) readPort.data := regFile(readPort.addr)
} }
dontTouch(regFile)
} }
object RegisterFile { object RegisterFile {

2
npc/core/src/test/scala/Main.scala
View file

@ -39,7 +39,7 @@ class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
} }
} }
"should compile" in { "should compile" in {
test(new Flow).withAnnotations(Seq(WriteVcdAnnotation)) { c => test(new Flow) { c =>
c.clock.step(1) c.clock.step(1)
} }
} }