From cb2ecd29ac7c3049a527f8abedb64f90e858e7d4 Mon Sep 17 00:00:00 2001
From: tracer-ysyx <tracer@ysyx.org>
Date: Wed, 13 Mar 2024 10:19:24 +0800
Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?=
 =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.6.19=20#1-?=
 =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:11?=
 =?UTF-8?q?=20UTC=202024=20x86=5F64=20GNU/Linux=20=20=2010:19:24=20=20up?=
 =?UTF-8?q?=204=20days=20=201:09,=20=202=20users,=20=20load=20average:=201?=
 =?UTF-8?q?.63,=201.47,=201.02?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 npc/core/anno.json                         |  4 ++++
 npc/core/src/main/scala/Main.scala         | 10 +++++-----
 npc/core/src/main/scala/RegisterFile.scala |  1 +
 npc/core/src/test/scala/Main.scala         |  2 +-
 4 files changed, 11 insertions(+), 6 deletions(-)
 create mode 100644 npc/core/anno.json

diff --git a/npc/core/anno.json b/npc/core/anno.json
new file mode 100644
index 0000000..57608d3
--- /dev/null
+++ b/npc/core/anno.json
@@ -0,0 +1,4 @@
+[{
+    "class": "firrtl.transforms.DontTouchAnnotation",
+    "target": "~Flow|Control"
+}]
diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index 71c2a63..5e5288c 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -47,15 +47,13 @@ class Control(width: Int) extends Module {
   val ControlMapping: Array[(BitPat, T)] = Array(
     //     Regs                       :: PC         :: Exe
     //     writeEnable :: writeSelect :: srcSelect  ::
-    (addi, false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil),
-    // ("", false.B :: rAluOut :: pStaticNpc :: aOpNop :: HNil),
+    (addi, false.B     :: rAluOut     :: pStaticNpc :: aOpAdd :: HNil),
   )
   def toBits(t: T): BitPat = {
     val list: List[Data] = t.toList
-    list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduce(_ ## _)
+    list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _)
   }
 
-  // val default = toBits(false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil).getWidth
   val default = BitPat("b???????")
 
   reg.writeEnable := false.B
@@ -90,7 +88,7 @@ class Flow extends Module {
     numReadPorts = 2,
     numWritePorts = 1,
     numReadwritePorts = 0,
-    // memoryFile = HexMemoryFile(memoryFile)
+    memoryFile = HexMemoryFile("../resource/addi.txt")
   )
   val control = Module(new Control(32))
   val reg = RegisterFile(32, dataType, 2, 2)
@@ -128,4 +126,6 @@ class Flow extends Module {
 
   alu.in.a := reg.out.src(0)
   alu.in.b := reg.out.src(1)
+  printf("Yes\n")
+  dontTouch(control.out)
 }
diff --git a/npc/core/src/main/scala/RegisterFile.scala b/npc/core/src/main/scala/RegisterFile.scala
index 00bf529..509ceaa 100644
--- a/npc/core/src/main/scala/RegisterFile.scala
+++ b/npc/core/src/main/scala/RegisterFile.scala
@@ -66,6 +66,7 @@ class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends
   for (readPort <- readPorts) {
     readPort.data := regFile(readPort.addr)
   }
+  dontTouch(regFile)
 }
 
 object RegisterFile {
diff --git a/npc/core/src/test/scala/Main.scala b/npc/core/src/test/scala/Main.scala
index 8477d57..0cab4ef 100644
--- a/npc/core/src/test/scala/Main.scala
+++ b/npc/core/src/test/scala/Main.scala
@@ -39,7 +39,7 @@ class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
     }
   }
   "should compile" in {
-    test(new Flow).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
+    test(new Flow) { c =>
       c.clock.step(1)
     }
   }