> build_flow_VFlow

ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  11:21:34  up   0:57,  2 users,  load average: 1.43, 0.78, 0.48

npc/core/src/main/scala/Main.scala

@@ -88,7 +88,7 @@ class Flow extends Module {
     numReadPorts = 2,
     numWritePorts = 1,
     numReadwritePorts = 0,
-    memoryFile = HexMemoryFile("../resource/addi.txt")
+    memoryFile = HexMemoryFile("./resource/addi.txt")
   )
   val control = Module(new Control(32))
   val reg = RegisterFile(32, dataType, 2, 2)

npc/waveform.vcd

@@ -0,0 +1,232 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module TOP $end
+  $var wire 1 M clock $end
+  $var wire 1 N reset $end
+  $scope module Flow $end
+   $var wire 1 M clock $end
+   $var wire 1 N reset $end
+   $scope module alu $end
+    $var wire 4 O control_op [3:0] $end
+    $var wire 32 # in_a [31:0] $end
+    $var wire 32 $ in_b [31:0] $end
+    $var wire 32 % out_result [31:0] $end
+   $upscope $end
+   $scope module control $end
+    $var wire 1 P reg_writeEnable $end
+    $var wire 1 P reg_writeSelect $end
+    $var wire 1 P pc_srcSelect $end
+    $var wire 4 O alu_op [3:0] $end
+    $var wire 7 Q out [6:0] $end
+   $upscope $end
+   $scope module pc $end
+    $var wire 1 M clock $end
+    $var wire 1 N reset $end
+    $var wire 1 P control_srcSelect $end
+    $var wire 32 & in_pcSrcs_0 [31:0] $end
+    $var wire 32 % in_pcSrcs_1 [31:0] $end
+    $var wire 32 ' out [31:0] $end
+    $var wire 32 ' pc [31:0] $end
+   $upscope $end
+   $scope module ram_mem_ext $end
+    $var wire 10 ( R0_addr [9:0] $end
+    $var wire 1 R R0_en $end
+    $var wire 1 M R0_clk $end
+    $var wire 32 ) R0_data [31:0] $end
+   $upscope $end
+   $scope module reg_core $end
+    $var wire 1 M clock $end
+    $var wire 1 N reset $end
+    $var wire 1 P writePort_enable $end
+    $var wire 5 * writePort_addr [4:0] $end
+    $var wire 32 % writePort_data [31:0] $end
+    $var wire 5 + readPorts_0_addr [4:0] $end
+    $var wire 32 # readPorts_0_data [31:0] $end
+    $var wire 5 , readPorts_1_addr [4:0] $end
+    $var wire 32 $ readPorts_1_data [31:0] $end
+    $var wire 32 - regFile_0 [31:0] $end
+    $var wire 32 . regFile_1 [31:0] $end
+    $var wire 32 / regFile_2 [31:0] $end
+    $var wire 32 0 regFile_3 [31:0] $end
+    $var wire 32 1 regFile_4 [31:0] $end
+    $var wire 32 2 regFile_5 [31:0] $end
+    $var wire 32 3 regFile_6 [31:0] $end
+    $var wire 32 4 regFile_7 [31:0] $end
+    $var wire 32 5 regFile_8 [31:0] $end
+    $var wire 32 6 regFile_9 [31:0] $end
+    $var wire 32 7 regFile_10 [31:0] $end
+    $var wire 32 8 regFile_11 [31:0] $end
+    $var wire 32 9 regFile_12 [31:0] $end
+    $var wire 32 : regFile_13 [31:0] $end
+    $var wire 32 ; regFile_14 [31:0] $end
+    $var wire 32 < regFile_15 [31:0] $end
+    $var wire 32 = regFile_16 [31:0] $end
+    $var wire 32 > regFile_17 [31:0] $end
+    $var wire 32 ? regFile_18 [31:0] $end
+    $var wire 32 @ regFile_19 [31:0] $end
+    $var wire 32 A regFile_20 [31:0] $end
+    $var wire 32 B regFile_21 [31:0] $end
+    $var wire 32 C regFile_22 [31:0] $end
+    $var wire 32 D regFile_23 [31:0] $end
+    $var wire 32 E regFile_24 [31:0] $end
+    $var wire 32 F regFile_25 [31:0] $end
+    $var wire 32 G regFile_26 [31:0] $end
+    $var wire 32 H regFile_27 [31:0] $end
+    $var wire 32 I regFile_28 [31:0] $end
+    $var wire 32 J regFile_29 [31:0] $end
+    $var wire 32 K regFile_30 [31:0] $end
+    $var wire 32 L regFile_31 [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
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