From b3b2495a7ba01d55869fd27ec3740e54aae23b68 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Wed, 13 Mar 2024 11:21:34 +0800 Subject: [PATCH] =?UTF-8?q?>=20build=5Fflow=5FVFlow=20=20ysyx=5F22040000?= =?UTF-8?q?=20=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.6.19=20?= =?UTF-8?q?#1-NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:1?= =?UTF-8?q?1=20UTC=202024=20x86=5F64=20GNU/Linux=20=20=2011:21:34=20=20up?= =?UTF-8?q?=20=20=200:57,=20=202=20users,=20=20load=20average:=201.43,=200?= =?UTF-8?q?.78,=200.48?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/Main.scala | 2 +- npc/waveform.vcd | 232 +++++++++++++++++++++++++++++ 2 files changed, 233 insertions(+), 1 deletion(-) create mode 100644 npc/waveform.vcd diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index 72ce8a0..b56b939 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -88,7 +88,7 @@ class Flow extends Module { numReadPorts = 2, numWritePorts = 1, numReadwritePorts = 0, - memoryFile = HexMemoryFile("../resource/addi.txt") + memoryFile = HexMemoryFile("./resource/addi.txt") ) val control = Module(new Control(32)) val reg = RegisterFile(32, dataType, 2, 2) diff --git a/npc/waveform.vcd b/npc/waveform.vcd new file mode 100644 index 0000000..6592a48 --- /dev/null +++ b/npc/waveform.vcd @@ -0,0 +1,232 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module TOP $end + $var wire 1 M clock $end + $var wire 1 N reset $end + $scope module Flow $end + $var wire 1 M clock $end + $var wire 1 N reset $end + $scope module alu $end + $var wire 4 O control_op [3:0] $end + $var wire 32 # in_a [31:0] $end + $var wire 32 $ in_b [31:0] $end + $var wire 32 % out_result [31:0] $end + $upscope $end + $scope module control $end + $var wire 1 P reg_writeEnable $end + $var wire 1 P reg_writeSelect $end + $var wire 1 P pc_srcSelect $end + $var wire 4 O alu_op [3:0] $end + $var wire 7 Q out [6:0] $end + $upscope $end + $scope module pc $end + $var wire 1 M clock $end + $var wire 1 N reset $end + $var wire 1 P control_srcSelect $end + $var wire 32 & in_pcSrcs_0 [31:0] $end + $var wire 32 % in_pcSrcs_1 [31:0] $end + $var wire 32 ' out [31:0] $end + $var wire 32 ' pc [31:0] $end + $upscope $end + $scope module ram_mem_ext $end + $var wire 10 ( R0_addr [9:0] $end + $var wire 1 R R0_en $end + $var wire 1 M R0_clk $end + $var wire 32 ) R0_data [31:0] $end + $upscope $end + $scope module reg_core $end + $var wire 1 M clock $end + $var wire 1 N reset $end + $var wire 1 P writePort_enable $end + $var wire 5 * writePort_addr [4:0] $end + $var wire 32 % writePort_data [31:0] $end + $var wire 5 + readPorts_0_addr [4:0] $end + $var wire 32 # readPorts_0_data [31:0] $end + $var wire 5 , readPorts_1_addr [4:0] $end + $var wire 32 $ readPorts_1_data [31:0] $end + $var wire 32 - regFile_0 [31:0] $end + $var wire 32 . regFile_1 [31:0] $end + $var wire 32 / regFile_2 [31:0] $end + $var wire 32 0 regFile_3 [31:0] $end + $var wire 32 1 regFile_4 [31:0] $end + $var wire 32 2 regFile_5 [31:0] $end + $var wire 32 3 regFile_6 [31:0] $end + $var wire 32 4 regFile_7 [31:0] $end + $var wire 32 5 regFile_8 [31:0] $end + $var wire 32 6 regFile_9 [31:0] $end + $var wire 32 7 regFile_10 [31:0] $end + $var wire 32 8 regFile_11 [31:0] $end + $var wire 32 9 regFile_12 [31:0] $end + $var wire 32 : regFile_13 [31:0] $end + $var wire 32 ; regFile_14 [31:0] $end + $var wire 32 < regFile_15 [31:0] $end + $var wire 32 = regFile_16 [31:0] $end + $var wire 32 > regFile_17 [31:0] $end + $var wire 32 ? regFile_18 [31:0] $end + $var wire 32 @ regFile_19 [31:0] $end + $var wire 32 A regFile_20 [31:0] $end + $var wire 32 B regFile_21 [31:0] $end + $var wire 32 C regFile_22 [31:0] $end + $var wire 32 D regFile_23 [31:0] $end + $var wire 32 E regFile_24 [31:0] $end + $var wire 32 F regFile_25 [31:0] $end + $var wire 32 G regFile_26 [31:0] $end + $var wire 32 H regFile_27 [31:0] $end + $var wire 32 I regFile_28 [31:0] $end + $var wire 32 J regFile_29 [31:0] $end + $var wire 32 K regFile_30 [31:0] $end + $var wire 32 L regFile_31 [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 # +b00000000000000000000000000000000 $ +b00000000000000000000000000000000 % +b00000000000000000000000000000100 & +b00000000000000000000000000000000 ' +b0000000000 ( +b00000000000000000000000000000000 ) +b00000 * +b00000 + +b00000 , +b00000000000000000000000000000000 - +b00000000000000000000000000000000 . +b00000000000000000000000000000000 / +b00000000000000000000000000000000 0 +b00000000000000000000000000000000 1 +b00000000000000000000000000000000 2 +b00000000000000000000000000000000 3 +b00000000000000000000000000000000 4 +b00000000000000000000000000000000 5 +b00000000000000000000000000000000 6 +b00000000000000000000000000000000 7 +b00000000000000000000000000000000 8 +b00000000000000000000000000000000 9 +b00000000000000000000000000000000 : +b00000000000000000000000000000000 ; +b00000000000000000000000000000000 < +b00000000000000000000000000000000 = +b00000000000000000000000000000000 > +b00000000000000000000000000000000 ? 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