> sim RTL

ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 17:29:41  up  20:27,  2 users,  load average: 1.23, 1.01, 0.86
This commit is contained in:
tracer-ysyx 2023-12-23 17:29:41 +08:00 committed by xinyangli
parent 24f8dfbf52
commit a315f9ac2b
13 changed files with 3 additions and 1 deletions

View file

@ -2,6 +2,8 @@ VERILATOR := verilator
VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(wildcard csrc/*.cpp)
PREFIX ?= .
OBJDIR := $(PREFIX)/obj
all:
@echo "Write this Makefile by your self."
@ -11,6 +13,6 @@ sim: obj_dir
@echo "Write this Makefile by your self."
obj_dir: $(VSRC) $(CPPSRC)
$(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $@
$(VERILATOR) $(VSRC:%=--cc %) $(CPPSRC:%=--exe %) --Mdir $(OBJDIR)
include ../Makefile