create Makefile for example in verilator manual

npc/Makefile

@@ -1,8 +1,31 @@
-all:
+VSRC := $(wildcard vsrc/*.v)
-	@echo "Write this Makefile by your self."
+CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
+PREFIX ?= build
+OBJDIR := $(PREFIX)/obj
+SUBMAKE := $(OBJDIR)/Vexample.mk
+VERILATOR_FLAGS := --cc --exe
 
-sim:
+all: sim
+
+sim: VERILATOR_FLAGS += --trace
+sim: $(VSRC) $(CPPSRC) $(OBJDIR)/Vexample
 	$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
-	@echo "Write this Makefile by your self."
+	@echo "Running" $(OBJDIR)/Vexample "..."
+	@echo "================================"
+	@$(OBJDIR)/Vexample
+	
+$(OBJDIR)/Vexample: $(SUBMAKE)
+	$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
+	
+$(SUBMAKE): $(VSRC) $(CPPSRC) $(OBJDIR)
+	verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
 
 include ../Makefile
+
+.PHONY: clean 
+
+clean: 
+	$(RM) -r $(OBJDIR)

npc/csrc/main.cpp

@@ -1,6 +1,32 @@
-#include <stdio.h>
+#include <cstdlib>
+#include <cassert>
+#include <cstdlib>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include "Vexample.h"
 
-int main() {
+#define MAX_SIM_TIME 100
-  printf("Hello, ysyx!\n");
+
-  return 0;
+int main(int argc, char **argv, char **env) {
+    int sim_time = 0;
+    Verilated::commandArgs(argc, argv);
+    Vexample *top = new Vexample;
+
+    Verilated::traceEverOn(true);
+    VerilatedVcdC *m_trace = new VerilatedVcdC; 
+    top->trace(m_trace, 5);
+    m_trace->open("waveform.vcd");
+    for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
+        int a = rand() & 1;
+        int b = rand() & 1;
+        top->a = a;
+        top->b = b;
+        top->eval();
+        printf("a = %d, b = %d, f = %d\n", a, b, top->f);
+        assert(top->f == (a ^ b));
+        m_trace->dump(sim_time);
+    }
+    m_trace->close();
+    delete top;
+    exit(EXIT_SUCCESS);
 }

npc/vsrc/example.v

@@ -1,2 +1,7 @@
-module example();
+module top(
-endmodule
+  input a,
+  input b,
+  output f
+);
+  assign f = a ^ b;
+endmodule