> nvboard
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 17:23:05 up 2:09, 2 users, load average: 2.15, 1.50, 1.16
This commit is contained in:
tracer-ysyx
parent
5feabac34d
commit
8dfae1f22d
6 changed files with 70 additions and 40 deletions
1
npc/.envrc
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1
npc/.envrc
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@ -0,0 +1 @@
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use flake
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11
npc/.gitignore
vendored
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npc/.gitignore
vendored
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@ -1,6 +1,3 @@
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*.*
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*
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!*/
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!Makefile
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!*.mk
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!*.[cSh]
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@ -13,6 +10,14 @@ build/
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*.class
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*.log
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.cache/
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.bsp/
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.bloop/
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.metals/
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# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
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hs_err_pid*
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.vscode/
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.direnv/
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compile_commands.json
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2
npc/.scalafmt.conf
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npc/.scalafmt.conf
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@ -0,0 +1,2 @@
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version = "3.7.15"
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runner.dialect = scala213
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66
npc/Makefile
66
npc/Makefile
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@ -1,42 +1,70 @@
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NVBOARD_HOME ?= $(abspath ../nvboard)
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PREFIX ?= build
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OBJDIR := $(PREFIX)/obj
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TARGET := $(OBJDIR)/Vexample
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CHISEL_VDIR := $(PREFIX)/chisel
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VSRC := $(wildcard vsrc/*.v)
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CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
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SUBMAKE := $(OBJDIR)/Vexample.mk
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SUBMAKE = $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
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VERILATOR_FLAGS := --cc --exe
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LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
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CHISEL_TOP_PACKAGE := learning
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CHISEL_TOP_MODULE := Main
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CHISEL_TARGET := verilog
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# Pretty printing
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MAKEFLAGS += --no-print-directory
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GREEN=\e[32m
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NC=\e[0m
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define colorize
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printf '$(GREEN)'$(1)'$(NC) $(2)\n'
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endef
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all: sim-bin nvboard-bin
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$(OBJDIR)/Vexample: $(SUBMAKE)
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$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
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$(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
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@$(call colorize,"SUBMAKE",$^)
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$(MAKE) -s -C $(OBJDIR) -f $(notdir $(SUBMAKE)) V$(CHISEL_TOP_MODULE)
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$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR)
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verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS)
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$(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src
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@$(call colorize,"VERILATOR",$^)
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verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
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$(OBJDIR):
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mkdir -p $(OBJDIR)
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sim-bin: VERILATOR_FLAGS += --trace
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sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample
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$(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
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@$(call colorize,"CIRCT",$^)
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sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)"
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SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
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NXDC_FILES := $(abspath constr/top.nxdc)
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$(SRC_AUTO_BIND): $(NXDC_FILES)
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NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
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compile_commands.json: clean
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$(MAKE) $(CHISEL_VDIR)/filelist.f
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$(RM) compile_commands.json
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bear --append -- $(MAKE) nvboard-bin
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bear --append -- $(MAKE) sim-bin
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.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard
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sim-bin: VERILATOR_FLAGS += --trace
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sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
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nvboard-bin: OBJDIR := $(PREFIX)/nvobj
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nvboard-bin: SUBMAKE := $(OBJDIR)/Vexample.mk
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nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
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# TODO: fix this awkward way to find nvboard.a
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nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
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nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
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nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample
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nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
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chisel-src: $(CHISEL_VDIR)/filelist.f
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$(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv))
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@echo "GENERATED: $(CHISEL_VSRC)"
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ifneq (,$(wildcard ../Makefile))
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include ../Makefile
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@ -51,22 +79,16 @@ git_trace_sim:
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git_trace_nvboard:
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$(call git_commit, "nvboard")
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.PHONY: clean nvboard sim compile_commands.json
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nvboard: OBJDIR := $(PREFIX)/nvobj
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nvboard: nvboard-bin git_trace_nvboard
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@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample
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@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
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sim: sim-bin git_trace_sim
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@echo "Running" $(OBJDIR)/Vexample "..."
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@echo "Running verilator sim ..."
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@echo "================================"
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@$(OBJDIR)/Vexample
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compile_commands.json: clean
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bear --output nvboard.json -- $(MAKE) nvboard-bin
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bear --output all.json -- $(MAKE) sim-bin
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jq -s ".[0] + .[1]" all.json nvboard.json > compile_commands.json
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$(RM) all.json nvboard.json
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@$(OBJDIR)/V$(CHISEL_TOP_MODULE)
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clean:
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$(RM) -r $(PREFIX)
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$(V).SILENT:
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@ -3,14 +3,14 @@
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#include <cstdlib>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include <Vexample.h>
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#include <VMain.h>
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const int MAX_SIM_TIME=100;
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int main(int argc, char **argv, char **env) {
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int sim_time = 0;
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Verilated::commandArgs(argc, argv);
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Vexample *top = new Vexample;
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VMain *top = new VMain;
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Verilated::traceEverOn(true);
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VerilatedVcdC *m_trace = new VerilatedVcdC;
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@ -18,16 +18,16 @@ int main(int argc, char **argv, char **env) {
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top->trace(m_trace, 5);
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m_trace->open("waveform.vcd");
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#endif
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for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
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CData sw = rand() & 0b11;
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top->sw = sw;
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top->eval();
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printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
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assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
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#ifdef VERILATOR_TRACE
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m_trace->dump(sim_time);
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#endif
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}
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// for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
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// CData sw = rand() & 0b11;
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// top->sw = sw;
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// top->eval();
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// printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
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// assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
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// #ifdef VERILATOR_TRACE
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// m_trace->dump(sim_time);
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// #endif
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// }
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#ifdef VERILATOR_TRACE
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m_trace->close();
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#endif
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@ -3,15 +3,15 @@
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#include <cstdlib>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include <Vexample.h>
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#include <VMain.h>
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#include <nvboard.h>
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const int MAX_SIM_TIME=100;
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void nvboard_bind_all_pins(Vexample* top);
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void nvboard_bind_all_pins(VMain* top);
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int main(int argc, char **argv, char **env) {
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Vexample *top = new Vexample;
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VMain* top = new VMain;
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nvboard_bind_all_pins(top);
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nvboard_init();
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