From 8dfae1f22d799b20855b58b150d5cd5ae3818aad Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Thu, 4 Jan 2024 17:23:05 +0800 Subject: [PATCH] =?UTF-8?q?>=20nvboard=20ysyx=5F22040000=20=E6=9D=8E?= =?UTF-8?q?=E5=BF=83=E6=9D=A8=20Linux=20calcite=206.1.69=20#1-NixOS=20SMP?= =?UTF-8?q?=20PREEMPT=5FDYNAMIC=20Wed=20Dec=2020=2016:00:29=20UTC=202023?= =?UTF-8?q?=20x86=5F64=20GNU/Linux=20=2017:23:05=20=20up=20=20=202:09,=20?= =?UTF-8?q?=202=20users,=20=20load=20average:=202.15,=201.50,=201.16?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/.envrc | 1 + npc/.gitignore | 11 +++++-- npc/.scalafmt.conf | 2 ++ npc/Makefile | 66 ++++++++++++++++++++++++++------------- npc/csrc/main.cpp | 24 +++++++------- npc/csrc_nvboard/main.cpp | 6 ++-- 6 files changed, 70 insertions(+), 40 deletions(-) create mode 100644 npc/.envrc create mode 100644 npc/.scalafmt.conf diff --git a/npc/.envrc b/npc/.envrc new file mode 100644 index 0000000..3550a30 --- /dev/null +++ b/npc/.envrc @@ -0,0 +1 @@ +use flake diff --git a/npc/.gitignore b/npc/.gitignore index 27545c4..89cb332 100644 --- a/npc/.gitignore +++ b/npc/.gitignore @@ -1,6 +1,3 @@ -*.* -* -!*/ !Makefile !*.mk !*.[cSh] @@ -13,6 +10,14 @@ build/ *.class *.log +.cache/ +.bsp/ +.bloop/ +.metals/ # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml hs_err_pid* + +.vscode/ +.direnv/ +compile_commands.json diff --git a/npc/.scalafmt.conf b/npc/.scalafmt.conf new file mode 100644 index 0000000..ee7753a --- /dev/null +++ b/npc/.scalafmt.conf @@ -0,0 +1,2 @@ +version = "3.7.15" +runner.dialect = scala213 \ No newline at end of file diff --git a/npc/Makefile b/npc/Makefile index a0771bd..dae477a 100644 --- a/npc/Makefile +++ b/npc/Makefile @@ -1,42 +1,70 @@ NVBOARD_HOME ?= $(abspath ../nvboard) PREFIX ?= build OBJDIR := $(PREFIX)/obj -TARGET := $(OBJDIR)/Vexample +CHISEL_VDIR := $(PREFIX)/chisel -VSRC := $(wildcard vsrc/*.v) CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp)) -SUBMAKE := $(OBJDIR)/Vexample.mk +SUBMAKE = $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk VERILATOR_FLAGS := --cc --exe LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image +CHISEL_TOP_PACKAGE := learning +CHISEL_TOP_MODULE := Main +CHISEL_TARGET := verilog + +# Pretty printing +MAKEFLAGS += --no-print-directory +GREEN=\e[32m +NC=\e[0m +define colorize + printf '$(GREEN)'$(1)'$(NC) $(2)\n' +endef + all: sim-bin nvboard-bin -$(OBJDIR)/Vexample: $(SUBMAKE) - $(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample +$(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE) + @$(call colorize,"SUBMAKE",$^) + $(MAKE) -s -C $(OBJDIR) -f $(notdir $(SUBMAKE)) V$(CHISEL_TOP_MODULE) -$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR) - verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS) +$(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src + @$(call colorize,"VERILATOR",$^) + verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS) $(OBJDIR): mkdir -p $(OBJDIR) -sim-bin: VERILATOR_FLAGS += --trace -sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample +$(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala) + @$(call colorize,"CIRCT",$^) + sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)" SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp) NXDC_FILES := $(abspath constr/top.nxdc) $(SRC_AUTO_BIND): $(NXDC_FILES) NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@ +compile_commands.json: clean + $(MAKE) $(CHISEL_VDIR)/filelist.f + $(RM) compile_commands.json + bear --append -- $(MAKE) nvboard-bin + bear --append -- $(MAKE) sim-bin + +.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard + +sim-bin: VERILATOR_FLAGS += --trace +sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE) + nvboard-bin: OBJDIR := $(PREFIX)/nvobj -nvboard-bin: SUBMAKE := $(OBJDIR)/Vexample.mk +nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk # TODO: fix this awkward way to find nvboard.a nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g -nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample +nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE) +chisel-src: $(CHISEL_VDIR)/filelist.f + $(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv)) + @echo "GENERATED: $(CHISEL_VSRC)" ifneq (,$(wildcard ../Makefile)) include ../Makefile @@ -51,22 +79,16 @@ git_trace_sim: git_trace_nvboard: $(call git_commit, "nvboard") -.PHONY: clean nvboard sim compile_commands.json - nvboard: OBJDIR := $(PREFIX)/nvobj nvboard: nvboard-bin git_trace_nvboard - @NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample + @NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE) sim: sim-bin git_trace_sim - @echo "Running" $(OBJDIR)/Vexample "..." + @echo "Running verilator sim ..." @echo "================================" - @$(OBJDIR)/Vexample - -compile_commands.json: clean - bear --output nvboard.json -- $(MAKE) nvboard-bin - bear --output all.json -- $(MAKE) sim-bin - jq -s ".[0] + .[1]" all.json nvboard.json > compile_commands.json - $(RM) all.json nvboard.json + @$(OBJDIR)/V$(CHISEL_TOP_MODULE) clean: $(RM) -r $(PREFIX) + +$(V).SILENT: diff --git a/npc/csrc/main.cpp b/npc/csrc/main.cpp index f39a65b..f5ce360 100644 --- a/npc/csrc/main.cpp +++ b/npc/csrc/main.cpp @@ -3,14 +3,14 @@ #include #include #include -#include +#include const int MAX_SIM_TIME=100; int main(int argc, char **argv, char **env) { int sim_time = 0; Verilated::commandArgs(argc, argv); - Vexample *top = new Vexample; + VMain *top = new VMain; Verilated::traceEverOn(true); VerilatedVcdC *m_trace = new VerilatedVcdC; @@ -18,16 +18,16 @@ int main(int argc, char **argv, char **env) { top->trace(m_trace, 5); m_trace->open("waveform.vcd"); #endif - for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) { - CData sw = rand() & 0b11; - top->sw = sw; - top->eval(); - printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr); - assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) ); -#ifdef VERILATOR_TRACE - m_trace->dump(sim_time); -#endif - } +// for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) { +// CData sw = rand() & 0b11; +// top->sw = sw; +// top->eval(); +// printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr); +// assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) ); +// #ifdef VERILATOR_TRACE +// m_trace->dump(sim_time); +// #endif +// } #ifdef VERILATOR_TRACE m_trace->close(); #endif diff --git a/npc/csrc_nvboard/main.cpp b/npc/csrc_nvboard/main.cpp index 398f564..88843e2 100644 --- a/npc/csrc_nvboard/main.cpp +++ b/npc/csrc_nvboard/main.cpp @@ -3,15 +3,15 @@ #include #include #include -#include +#include #include const int MAX_SIM_TIME=100; -void nvboard_bind_all_pins(Vexample* top); +void nvboard_bind_all_pins(VMain* top); int main(int argc, char **argv, char **env) { - Vexample *top = new Vexample; + VMain* top = new VMain; nvboard_bind_all_pins(top); nvboard_init();