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> compile NEMU

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ysyx_22040000 李心杨
Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
 11:25:20  up  21:01,  2 users,  load average: 0.85, 3.11, 2.77
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tracer-ysyx 2024-03-26 11:25:20 +08:00 committed by xinyangli
parent 38da9c425a
commit 8a58dfc68a
2 changed files with 4 additions and 2 deletions
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nemu/.result.tmp Normal file
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6
npc/core/src/main/scala/Main.scala
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@ -4,8 +4,7 @@ import chisel3._
import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse} import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
import chisel3.util.{SRAM} import chisel3.util.{SRAM}
import chisel3.stage.ChiselOption import chisel3.stage.ChiselOption
import npc.util.KeyboardSegController import npc.util.{ KeyboardSegController, RegisterFile }
import flowpc.components.RegisterFile
import flowpc.components.ProgramCounter import flowpc.components.ProgramCounter
class Switch extends Module { class Switch extends Module {
@ -34,9 +33,12 @@ class Keyboard extends Module {
io.segs := seg_handler.io.segs io.segs := seg_handler.io.segs
} }
<<<<<<< Updated upstream
=======
class Flowpc extends Module { class Flowpc extends Module {
val io = IO(new Bundle { }) val io = IO(new Bundle { })
val register_file = new RegisterFile(readPorts = 2); val register_file = new RegisterFile(readPorts = 2);
val pc = new ProgramCounter(32); val pc = new ProgramCounter(32);
val adder = new SRAM() val adder = new SRAM()
} }
>>>>>>> Stashed changes