diff --git a/nemu/.result.tmp b/nemu/.result.tmp
new file mode 100644
index 0000000..e69de29
diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index d4f38ec..95b9e61 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -4,8 +4,7 @@ import chisel3._
 import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
 import chisel3.util.{SRAM}
 import chisel3.stage.ChiselOption
-import npc.util.KeyboardSegController
-import flowpc.components.RegisterFile
+import npc.util.{ KeyboardSegController, RegisterFile }
 import flowpc.components.ProgramCounter
 
 class Switch extends Module {
@@ -34,9 +33,12 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
+<<<<<<< Updated upstream
+=======
 class Flowpc extends Module {
   val io = IO(new Bundle { })
   val register_file = new RegisterFile(readPorts = 2);
   val pc = new ProgramCounter(32);
   val adder = new SRAM()
 }
+>>>>>>> Stashed changes