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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  13:31:24  up   3:07,  2 users,  load average: 2.36, 1.52, 1.18
This commit is contained in:
tracer-ysyx 2024-03-13 13:31:24 +08:00 committed by xinyangli
parent 3fc7b061a9
commit 545c64c479
3 changed files with 28 additions and 25 deletions
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20
npc/core/src/main/scala/Main.scala
View file

@ -40,6 +40,11 @@ class Control(width: Int) extends Module {
type T = type T =
Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil
val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts
val dstList = dst.toList
val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
val slices = reversePrefixSum.zip(reversePrefixSum.tail)
import reg.WriteSelect._ import reg.WriteSelect._
import pc.SrcSelect._ import pc.SrcSelect._
import alu.OpSelect._ import alu.OpSelect._
@ -50,26 +55,15 @@ class Control(width: Int) extends Module {
// writeEnable :: writeSelect :: srcSelect :: // writeEnable :: writeSelect :: srcSelect ::
(addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil), (addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil),
) )
val default = BitPat.dontCare(dstList.map(_.getWidth).reduce(_ + _))
def toBits(t: T): BitPat = { def toBits(t: T): BitPat = {
val list: List[Data] = t.toList val list: List[Data] = t.toList
list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _) list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _)
} }
val default = BitPat("b????????")
reg.writeEnable := false.B
reg.writeSelect := reg.WriteSelect(0.U)
alu.op := alu.OpSelect(0.U)
pc.srcSelect := pc.SrcSelect(0.U)
val out = decoder( val out = decoder(
inst, inst,
TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default)) TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default))
println(out)
val dstList = dst.toList
val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
val slices = reversePrefixSum.zip(reversePrefixSum.tail)
val srcList = slices.map(s => out(s._1 - 1, s._2)) val srcList = slices.map(s => out(s._1 - 1, s._2))
srcList srcList

20
npc/resource/addi.txt
View file

@ -1,10 +1,10 @@
00084113 00114113
00084113 00114113
00084113 00114113
00084113 00114113
00084113 00114113
00084113 00114113
00084113 00114113
00084113 00114113
00084113 00114113
00084113 00114113

13
npc/waveform.vcd
View file

@ -136,11 +136,14 @@ b0000 P
0R 0R
b10000001 S b10000001 S
#1 #1
b00000000000000000000000000000001 $
b00000000000000000000000000000001 &
b10000000000000000000000000000100 ' b10000000000000000000000000000100 '
b10000000000000000000000000000000 ( b10000000000000000000000000000000 (
b00000000000010000100000100010011 * b00000000000100010100000100010011 *
b00010 + b00010 +
b10000 , b00010 ,
b00001 -
0N 0N
#2 #2
1N 1N
@ -162,9 +165,11 @@ b10000 ,
1N 1N
0O 0O
#11 #11
b00000000000000000000000000000001 #
b10000000000000000000000000001000 ' b10000000000000000000000000001000 '
b10000000000000000000000000000100 ( b10000000000000000000000000000100 (
b0000000100 ) b0000000100 )
b00000000000000000000000000000001 0
0N 0N
#12 #12
1N 1N
@ -183,12 +188,16 @@ b0000001100 )
#16 #16
1N 1N
#17 #17
b00000000000000000000000000000000 #
b00000000000000000000000000000000 $
b00000000000000000000000000000000 &
b10000000000000000000000000010100 ' b10000000000000000000000000010100 '
b10000000000000000000000000010000 ( b10000000000000000000000000010000 (
b0000010000 ) b0000010000 )
b00000000000000000000000000000000 * b00000000000000000000000000000000 *
b00000 + b00000 +
b00000 , b00000 ,
b00000 -
0N 0N
#18 #18
1N 1N