diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index 2ac6b7e..a78581f 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -40,6 +40,11 @@ class Control(width: Int) extends Module { type T = Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts + + val dstList = dst.toList + val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse + val slices = reversePrefixSum.zip(reversePrefixSum.tail) + import reg.WriteSelect._ import pc.SrcSelect._ import alu.OpSelect._ @@ -50,26 +55,15 @@ class Control(width: Int) extends Module { // writeEnable :: writeSelect :: srcSelect :: (addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil), ) + val default = BitPat.dontCare(dstList.map(_.getWidth).reduce(_ + _)) + def toBits(t: T): BitPat = { val list: List[Data] = t.toList list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _) } - - val default = BitPat("b????????") - - reg.writeEnable := false.B - reg.writeSelect := reg.WriteSelect(0.U) - alu.op := alu.OpSelect(0.U) - pc.srcSelect := pc.SrcSelect(0.U) - val out = decoder( inst, TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default)) - println(out) - - val dstList = dst.toList - val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse - val slices = reversePrefixSum.zip(reversePrefixSum.tail) val srcList = slices.map(s => out(s._1 - 1, s._2)) srcList diff --git a/npc/resource/addi.txt b/npc/resource/addi.txt index 55960bf..8eb11e4 100644 --- a/npc/resource/addi.txt +++ b/npc/resource/addi.txt @@ -1,10 +1,10 @@ -00084113 -00084113 -00084113 -00084113 -00084113 -00084113 -00084113 -00084113 -00084113 -00084113 +00114113 +00114113 +00114113 +00114113 +00114113 +00114113 +00114113 +00114113 +00114113 +00114113 diff --git a/npc/waveform.vcd b/npc/waveform.vcd index a3bc5ab..7f9ab17 100644 --- a/npc/waveform.vcd +++ b/npc/waveform.vcd @@ -136,11 +136,14 @@ b0000 P 0R b10000001 S #1 +b00000000000000000000000000000001 $ +b00000000000000000000000000000001 & b10000000000000000000000000000100 ' b10000000000000000000000000000000 ( -b00000000000010000100000100010011 * +b00000000000100010100000100010011 * b00010 + -b10000 , +b00010 , +b00001 - 0N #2 1N @@ -162,9 +165,11 @@ b10000 , 1N 0O #11 +b00000000000000000000000000000001 # b10000000000000000000000000001000 ' b10000000000000000000000000000100 ( b0000000100 ) +b00000000000000000000000000000001 0 0N #12 1N @@ -183,12 +188,16 @@ b0000001100 ) #16 1N #17 +b00000000000000000000000000000000 # +b00000000000000000000000000000000 $ +b00000000000000000000000000000000 & b10000000000000000000000000010100 ' b10000000000000000000000000010000 ( b0000010000 ) b00000000000000000000000000000000 * b00000 + b00000 , +b00000 - 0N #18 1N