build: add nvboard support to led light
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parent
8e861a43fb
commit
38818f6f66
5 changed files with 108 additions and 28 deletions
72
npc/Makefile
72
npc/Makefile
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@ -1,31 +1,71 @@
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VSRC := $(wildcard vsrc/*.v)
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CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
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NVBOARD_HOME ?= $(abspath ../nvboard)
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PREFIX ?= build
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OBJDIR := $(PREFIX)/obj
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TARGET := $(OBJDIR)/Vexample
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VSRC := $(wildcard vsrc/*.v)
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CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
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SUBMAKE := $(OBJDIR)/Vexample.mk
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VERILATOR_FLAGS := --cc --exe
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LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
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all: sim
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sim: VERILATOR_FLAGS += --trace
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sim: $(VSRC) $(CPPSRC) $(OBJDIR)/Vexample
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$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
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@echo "Running" $(OBJDIR)/Vexample "..."
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@echo "================================"
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@$(OBJDIR)/Vexample
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all: sim-bin nvboard-bin
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$(OBJDIR)/Vexample: $(SUBMAKE)
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$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
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$(SUBMAKE): $(VSRC) $(CPPSRC) $(OBJDIR)
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verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
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$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR)
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verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS)
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$(OBJDIR):
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mkdir -p $(OBJDIR)
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include ../Makefile
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sim-bin: VERILATOR_FLAGS += --trace
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sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample
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.PHONY: clean
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SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
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NXDC_FILES := $(abspath constr/top.nxdc)
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$(SRC_AUTO_BIND): $(NXDC_FILES)
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NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
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nvboard-bin: OBJDIR := $(PREFIX)/nvobj
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nvboard-bin: SUBMAKE := $(OBJDIR)/Vexample.mk
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# TODO: fix this awkward way to find nvboard.a
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nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
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nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g
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nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample
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ifneq (,$(wildcard ../Makefile))
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include ../Makefile
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else
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define git_commit # not in ICS subfolder, no tracing
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endef
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endif
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git_trace_sim:
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$(call git_commit, "sim RTL")
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git_trace_nvboard:
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$(call git_commit, "nvboard")
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.PHONY: clean nvboard sim compile_commands.json
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nvboard: nvboard-bin git_trace_nvboard
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@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample
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sim: sim-bin git_trace_sim
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@echo "Running" $(OBJDIR)/Vexample "..."
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@echo "================================"
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@$(OBJDIR)/Vexample
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compile_commands.json: clean
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bear --output nvboard.json -- $(MAKE) nvboard-bin
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bear --output all.json -- $(MAKE) sim-bin
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jq -s ".[0] + .[1]" all.json nvboard.json > compile_commands.json
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$(RM) all.json nvboard.json
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clean:
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$(RM) -r $(OBJDIR)
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$(RM) -r $(PREFIX)
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@ -3,9 +3,9 @@
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#include <cstdlib>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include "Vexample.h"
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#include <Vexample.h>
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#define MAX_SIM_TIME 100
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const int MAX_SIM_TIME=100;
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int main(int argc, char **argv, char **env) {
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int sim_time = 0;
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@ -14,19 +14,23 @@ int main(int argc, char **argv, char **env) {
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Verilated::traceEverOn(true);
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VerilatedVcdC *m_trace = new VerilatedVcdC;
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#ifdef VERILATOR_TRACE
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top->trace(m_trace, 5);
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m_trace->open("waveform.vcd");
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#endif
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for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
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int a = rand() & 1;
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int b = rand() & 1;
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top->a = a;
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top->b = b;
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CData sw = rand() & 0b11;
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top->sw = sw;
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top->eval();
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printf("a = %d, b = %d, f = %d\n", a, b, top->f);
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assert(top->f == (a ^ b));
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printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
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assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
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#ifdef VERILATOR_TRACE
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m_trace->dump(sim_time);
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#endif
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}
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#ifdef VERILATOR_TRACE
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m_trace->close();
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#endif
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delete top;
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exit(EXIT_SUCCESS);
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}
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23
npc/csrc_nvboard/main.cpp
Normal file
23
npc/csrc_nvboard/main.cpp
Normal file
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@ -0,0 +1,23 @@
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#include <cstdlib>
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#include <cassert>
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#include <cstdlib>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include <Vexample.h>
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#include <nvboard.h>
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const int MAX_SIM_TIME=100;
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void nvboard_bind_all_pins(Vexample* top);
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int main(int argc, char **argv, char **env) {
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Vexample *top = new Vexample;
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nvboard_bind_all_pins(top);
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nvboard_init();
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while (true) {
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nvboard_update();
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top->eval();
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}
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delete top;
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}
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@ -13,8 +13,22 @@
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verilator
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gtkwave
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gcc
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gdb
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jq
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bear
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clang-tools
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rnix-lsp
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];
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nativeBuildInputs = with pkgs; [
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python3
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];
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buildInputs = with pkgs; [
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SDL2
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SDL2_image
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];
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shellHook = ''
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export NEMU_HOME=/home/xin/repo/ysyx-workbench/nemu
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'';
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@ -1,7 +1,6 @@
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module top(
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input a,
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input b,
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output f
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input [1:0] sw,
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output ledr
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);
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assign f = a ^ b;
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assign ledr = sw[1] ^ sw[0];
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endmodule
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