From 38818f6f667878544057e8fc2912e01c7b31b51a Mon Sep 17 00:00:00 2001 From: xinyangli Date: Mon, 1 Jan 2024 14:41:31 +0800 Subject: [PATCH] build: add nvboard support to led light --- npc/Makefile | 72 ++++++++++++++++++++++++++++++--------- npc/csrc/main.cpp | 20 ++++++----- npc/csrc_nvboard/main.cpp | 23 +++++++++++++ npc/flake.nix | 14 ++++++++ npc/vsrc/example.v | 7 ++-- 5 files changed, 108 insertions(+), 28 deletions(-) create mode 100644 npc/csrc_nvboard/main.cpp diff --git a/npc/Makefile b/npc/Makefile index 4910019..ee02342 100644 --- a/npc/Makefile +++ b/npc/Makefile @@ -1,31 +1,71 @@ -VSRC := $(wildcard vsrc/*.v) -CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp)) +NVBOARD_HOME ?= $(abspath ../nvboard) PREFIX ?= build OBJDIR := $(PREFIX)/obj +TARGET := $(OBJDIR)/Vexample + +VSRC := $(wildcard vsrc/*.v) +CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp)) SUBMAKE := $(OBJDIR)/Vexample.mk + VERILATOR_FLAGS := --cc --exe +LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image -all: sim - -sim: VERILATOR_FLAGS += --trace -sim: $(VSRC) $(CPPSRC) $(OBJDIR)/Vexample - $(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!! - @echo "Running" $(OBJDIR)/Vexample "..." - @echo "================================" - @$(OBJDIR)/Vexample +all: sim-bin nvboard-bin $(OBJDIR)/Vexample: $(SUBMAKE) $(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample - -$(SUBMAKE): $(VSRC) $(CPPSRC) $(OBJDIR) - verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC) + +$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR) + verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS) $(OBJDIR): mkdir -p $(OBJDIR) -include ../Makefile +sim-bin: VERILATOR_FLAGS += --trace +sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample -.PHONY: clean +SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp) +NXDC_FILES := $(abspath constr/top.nxdc) +$(SRC_AUTO_BIND): $(NXDC_FILES) + NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@ + +nvboard-bin: OBJDIR := $(PREFIX)/nvobj +nvboard-bin: SUBMAKE := $(OBJDIR)/Vexample.mk +# TODO: fix this awkward way to find nvboard.a +nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a +nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g + +nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample + + +ifneq (,$(wildcard ../Makefile)) +include ../Makefile +else +define git_commit # not in ICS subfolder, no tracing +endef +endif + +git_trace_sim: + $(call git_commit, "sim RTL") + +git_trace_nvboard: + $(call git_commit, "nvboard") + +.PHONY: clean nvboard sim compile_commands.json + +nvboard: nvboard-bin git_trace_nvboard + @NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample + +sim: sim-bin git_trace_sim + @echo "Running" $(OBJDIR)/Vexample "..." + @echo "================================" + @$(OBJDIR)/Vexample + +compile_commands.json: clean + bear --output nvboard.json -- $(MAKE) nvboard-bin + bear --output all.json -- $(MAKE) sim-bin + jq -s ".[0] + .[1]" all.json nvboard.json > compile_commands.json + $(RM) all.json nvboard.json clean: - $(RM) -r $(OBJDIR) + $(RM) -r $(PREFIX) diff --git a/npc/csrc/main.cpp b/npc/csrc/main.cpp index 70e48e4..f39a65b 100644 --- a/npc/csrc/main.cpp +++ b/npc/csrc/main.cpp @@ -3,9 +3,9 @@ #include #include #include -#include "Vexample.h" +#include -#define MAX_SIM_TIME 100 +const int MAX_SIM_TIME=100; int main(int argc, char **argv, char **env) { int sim_time = 0; @@ -14,19 +14,23 @@ int main(int argc, char **argv, char **env) { Verilated::traceEverOn(true); VerilatedVcdC *m_trace = new VerilatedVcdC; +#ifdef VERILATOR_TRACE top->trace(m_trace, 5); m_trace->open("waveform.vcd"); +#endif for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) { - int a = rand() & 1; - int b = rand() & 1; - top->a = a; - top->b = b; + CData sw = rand() & 0b11; + top->sw = sw; top->eval(); - printf("a = %d, b = %d, f = %d\n", a, b, top->f); - assert(top->f == (a ^ b)); + printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr); + assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) ); +#ifdef VERILATOR_TRACE m_trace->dump(sim_time); +#endif } +#ifdef VERILATOR_TRACE m_trace->close(); +#endif delete top; exit(EXIT_SUCCESS); } diff --git a/npc/csrc_nvboard/main.cpp b/npc/csrc_nvboard/main.cpp new file mode 100644 index 0000000..398f564 --- /dev/null +++ b/npc/csrc_nvboard/main.cpp @@ -0,0 +1,23 @@ +#include +#include +#include +#include +#include +#include +#include + +const int MAX_SIM_TIME=100; + +void nvboard_bind_all_pins(Vexample* top); + +int main(int argc, char **argv, char **env) { + Vexample *top = new Vexample; + + nvboard_bind_all_pins(top); + nvboard_init(); + while (true) { + nvboard_update(); + top->eval(); + } + delete top; +} \ No newline at end of file diff --git a/npc/flake.nix b/npc/flake.nix index 3c5c8af..2979d67 100644 --- a/npc/flake.nix +++ b/npc/flake.nix @@ -13,8 +13,22 @@ verilator gtkwave gcc + gdb + jq bear + clang-tools + rnix-lsp ]; + + nativeBuildInputs = with pkgs; [ + python3 + ]; + + buildInputs = with pkgs; [ + SDL2 + SDL2_image + ]; + shellHook = '' export NEMU_HOME=/home/xin/repo/ysyx-workbench/nemu ''; diff --git a/npc/vsrc/example.v b/npc/vsrc/example.v index 38b2b39..4d290d4 100644 --- a/npc/vsrc/example.v +++ b/npc/vsrc/example.v @@ -1,7 +1,6 @@ module top( - input a, - input b, - output f + input [1:0] sw, + output ledr ); - assign f = a ^ b; + assign ledr = sw[1] ^ sw[0]; endmodule \ No newline at end of file