xin/ysyx-workbench
1
0
Fork 0
Code Issues Pull requests 1 Projects Releases Packages Wiki Activity Actions

> configure(npc)

Browse source 
ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  21:19:07  up 3 days 12:09,  2 users,  load average: 1.25, 1.77, 1.50
This commit is contained in:
tracer-ysyx 2024-03-12 21:19:07 +08:00 committed by xinyangli
parent 7d581b47eb
commit 2914694445
2 changed files with 3 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
npc/core/src/main/scala/Main.scala
View file

@ -89,7 +89,7 @@ class Control(width: Int) extends Module {
import flow.components.{RegisterFile, RegFileInterface, ProgramCounter, ALU}
import chisel3.util.experimental.loadMemoryFromFileInline
class Flow(memoryFile: String) extends Module {
class Flow extends Module {
// val dataType = UInt(32.W)
val ram = SRAM(
@ -98,7 +98,7 @@ class Flow(memoryFile: String) extends Module {
numReadPorts = 2,
numWritePorts = 1,
numReadwritePorts = 0,
memoryFile = HexMemoryFile(memoryFile)
// memoryFile = HexMemoryFile(memoryFile)
)
val control = Module(new Control(32))
val reg = RegisterFile(32, UInt(32.W), 2, 2)

3
npc/core/src/test/scala/Main.scala
View file

@ -39,9 +39,8 @@ class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
}
}
"should compile" in {
test(new Flow("../resource/addi.txt")) { c =>
test(new Flow("../resource/addi.txt")).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
c.clock.step(1)
// c.clock.step(100)
}
}