diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index a9eb10e..b69b51f 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -89,7 +89,7 @@ class Control(width: Int) extends Module {
 
 import flow.components.{RegisterFile, RegFileInterface, ProgramCounter, ALU}
 import chisel3.util.experimental.loadMemoryFromFileInline
-class Flow(memoryFile: String) extends Module {
+class Flow extends Module {
   // val dataType = UInt(32.W)
 
   val ram = SRAM(
@@ -98,7 +98,7 @@ class Flow(memoryFile: String) extends Module {
     numReadPorts = 2,
     numWritePorts = 1,
     numReadwritePorts = 0,
-    memoryFile = HexMemoryFile(memoryFile)
+    // memoryFile = HexMemoryFile(memoryFile)
   )
   val control = Module(new Control(32))
   val reg = RegisterFile(32, UInt(32.W), 2, 2)
diff --git a/npc/core/src/test/scala/Main.scala b/npc/core/src/test/scala/Main.scala
index 6a04681..9c006f4 100644
--- a/npc/core/src/test/scala/Main.scala
+++ b/npc/core/src/test/scala/Main.scala
@@ -39,9 +39,8 @@ class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
     }
   }
   "should compile" in {
-    test(new Flow("../resource/addi.txt")) { c =>
+    test(new Flow("../resource/addi.txt")).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
       c.clock.step(1)
-      // c.clock.step(100)
     }
   }