build: move to cmake

This commit is contained in:
xinyangli 2024-01-05 23:50:26 +08:00
parent 38818f6f66
commit 1702da0a0a
11 changed files with 896 additions and 78 deletions

1
npc/.envrc Normal file
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@ -0,0 +1 @@
use flake

27
npc/.gitignore vendored
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@ -1,12 +1,17 @@
*.*
*
!*/
!Makefile
!*.mk
!*.[cSh]
!*.v
!*.cc
!*.cpp
!.gitignore
!README.md
build/ build/
**/project/
**/target/
*.class
*.log
.cache/
**/.bsp/
.bloop/
.metals/
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
hs_err_pid*
.vscode/
.direnv/
compile_commands.json

2
npc/.scalafmt.conf Normal file
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@ -0,0 +1,2 @@
version = "3.7.15"
runner.dialect = scala213

72
npc/CMakeLists.txt Normal file
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@ -0,0 +1,72 @@
cmake_minimum_required(VERSION 3.20)
project(npc)
set (CMAKE_CXX_STANDARD 11)
cmake_policy(SET CMP0144 NEW)
find_package(SDL2 REQUIRED)
find_package(SDL2_image REQUIRED)
find_package(verilator REQUIRED)
find_library(NVBOARD_LIBRARY NAMES nvboard)
find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
set(TOPMODULE "Switch")
set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")
file(GLOB_RECURSE SCALA_CORE_TEST_SOURCES "${SCALA_CORE}/src/test/scala/*.scala")
# Configure time verilog source generation for verilator
execute_process(
COMMAND sbt "runMain circt.stage.ChiselMain --target-dir ${CMAKE_CURRENT_BINARY_DIR}/vsrc --module ${CHISEL_MODULE_CLASS} --target verilog"
WORKING_DIRECTORY ${SCALA_CORE}
)
add_custom_command(
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v
COMMAND sbt "runMain circt.stage.ChiselMain --target-dir ${CMAKE_CURRENT_BINARY_DIR}/vsrc --module ${CHISEL_MODULE_CLASS} --target verilog"
WORKING_DIRECTORY ${SCALA_CORE}
DEPENDS ${SCALA_CORE_SOURCES}
)
add_custom_target(
ChiselBuild
DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v
)
# -- Build NVBoard executable
add_custom_command(
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/auto_bind.cpp
COMMAND auto_pin_bind ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc ${CMAKE_CURRENT_BINARY_DIR}/auto_bind.cpp
DEPENDS ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc
)
add_executable(V${TOPMODULE}_nvboard csrc_nvboard/main.cpp auto_bind.cpp)
verilate(V${TOPMODULE}_nvboard TRACE COVERAGE THREADS
TOP_MODULE ${TOPMODULE}
PREFIX V${TOPMODULE}
SOURCES ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v)
add_dependencies(V${TOPMODULE}_nvboard ChiselBuild)
target_include_directories(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_INCLUDE_DIR} ${SDL2_INCLUDE_DIRS})
target_link_libraries(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_LIBRARY} SDL2::SDL2 SDL2_image::SDL2_image)
install(TARGETS V${TOPMODULE}_nvboard)
# -- Build Verilator executable and add to test
add_executable(V${TOPMODULE} csrc/main.cpp)
verilate(V${TOPMODULE} TRACE COVERAGE THREADS
TOP_MODULE ${TOPMODULE}
PREFIX V${TOPMODULE}
SOURCES ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v)
add_dependencies(V${TOPMODULE} ChiselBuild)
enable_testing()
add_test(NAME V${TOPMODULE} COMMAND V${TOPMODULE})

View file

@ -1,28 +1,56 @@
NVBOARD_HOME ?= $(abspath ../nvboard) NVBOARD_HOME ?= $(abspath ../nvboard)
PREFIX ?= build PREFIX ?= build
OBJDIR := $(PREFIX)/obj CHISEL_VDIR := $(PREFIX)/chisel
TARGET := $(OBJDIR)/Vexample
VSRC := $(wildcard vsrc/*.v)
CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp)) CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
SUBMAKE := $(OBJDIR)/Vexample.mk
VERILATOR_FLAGS := --cc --exe VERILATOR_FLAGS := --cc --exe
LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
CHISEL_TOP_PACKAGE := learning
CHISEL_TOP_MODULE := Main
CHISEL_TARGET := verilog
SUBDIRS := obj nvobj
SUBDIRS := $(addprefix $(PREFIX),$(SUBDIRS))
SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# Pretty printing
MAKEFLAGS += --no-print-directory
GREEN := \e[32m
NC := \e[0m
define colorize
printf '$(GREEN)'$(1)'$(NC) $(2)\n'
endef
all: sim-bin nvboard-bin all: sim-bin nvboard-bin
$(OBJDIR)/Vexample: $(SUBMAKE) $(SUBDIRS):%: %/V$(CHISEL_TOP_MODULE).mk
$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
$(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR) $(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRCS) @$(call colorize,"SUBMAKE",$^)
$(MAKE) -s -C $(dir $@) -f $< $(notdir $@)
$(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src
@$(call colorize,"VERILATOR",$@)
verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
$(OBJDIR): $(OBJDIR):
mkdir -p $(OBJDIR) mkdir -p $@
sim-bin: VERILATOR_FLAGS += --trace $(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample @$(call colorize,"CIRCT",$^)
sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)"
compile_commands.json: clean
$(MAKE) $(CHISEL_VDIR)/filelist.f
$(RM) compile_commands.json
bear --append -- $(MAKE) nvboard-bin
bear --append -- $(MAKE) sim-bin
.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp) SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc) NXDC_FILES := $(abspath constr/top.nxdc)
@ -30,13 +58,19 @@ $(SRC_AUTO_BIND): $(NXDC_FILES)
NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@ NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
nvboard-bin: OBJDIR := $(PREFIX)/nvobj nvboard-bin: OBJDIR := $(PREFIX)/nvobj
nvboard-bin: SUBMAKE := $(OBJDIR)/Vexample.mk nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
# TODO: fix this awkward way to find nvboard.a # TODO: fix this awkward way to find nvboard.a
nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags) -g nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags)
nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
@echo $(SUBMAKE) $(OBJDIR)
nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
chisel-src: $(CHISEL_VDIR)/filelist.f
$(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv))
@echo "GENERATED: $(CHISEL_VSRC)"
ifneq (,$(wildcard ../Makefile)) ifneq (,$(wildcard ../Makefile))
include ../Makefile include ../Makefile
@ -51,21 +85,18 @@ git_trace_sim:
git_trace_nvboard: git_trace_nvboard:
$(call git_commit, "nvboard") $(call git_commit, "nvboard")
.PHONY: clean nvboard sim compile_commands.json nvboard: OBJDIR := $(PREFIX)/nvobj
nvboard: nvboard-bin git_trace_nvboard nvboard: nvboard-bin git_trace_nvboard
@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample @echo "Running NVBoard ..."
@echo "================================"
@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
sim: sim-bin git_trace_sim sim: sim-bin git_trace_sim
@echo "Running" $(OBJDIR)/Vexample "..." @echo "Running verilator sim ..."
@echo "================================" @echo "================================"
@$(OBJDIR)/Vexample @$(OBJDIR)/V$(CHISEL_TOP_MODULE)
compile_commands.json: clean
bear --output nvboard.json -- $(MAKE) nvboard-bin
bear --output all.json -- $(MAKE) sim-bin
jq -s ".[0] + .[1]" all.json nvboard.json > compile_commands.json
$(RM) all.json nvboard.json
clean: clean:
$(RM) -r $(PREFIX) $(RM) -r $(PREFIX)
$(V).SILENT:

622
npc/core/Makefile Normal file
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@ -0,0 +1,622 @@
# CMAKE generated file: DO NOT EDIT!
# Generated by "Unix Makefiles" Generator, CMake Version 3.27
# Default target executed when no arguments are given to make.
default_target: all
.PHONY : default_target
# Allow only one "make -f Makefile2" at a time, but pass parallelism.
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# Disable VCS-based implicit rules.
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# Disable VCS-based implicit rules.
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# Disable VCS-based implicit rules.
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# Disable VCS-based implicit rules.
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.SUFFIXES: .hpux_make_needs_suffix_list
# Command-line flag to silence nested $(MAKE).
$(VERBOSE)MAKESILENT = -s
#Suppress display of executed commands.
$(VERBOSE).SILENT:
# A target that is always out of date.
cmake_force:
.PHONY : cmake_force
#=============================================================================
# Set environment variables for the build.
# The shell in which to execute make rules.
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# The CMake executable.
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nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.o:
$(MAKE) $(MAKESILENT) -f CMakeFiles/VMain.dir/build.make CMakeFiles/VMain.dir/nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.o
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nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.i: nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.i
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.i
# target to preprocess a source file
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.i:
$(MAKE) $(MAKESILENT) -f CMakeFiles/VMain.dir/build.make CMakeFiles/VMain.dir/nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.i
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nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.s: nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.s
.PHONY : nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.s
# target to generate assembly for a file
nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.s:
$(MAKE) $(MAKESILENT) -f CMakeFiles/VMain.dir/build.make CMakeFiles/VMain.dir/nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.cpp.s
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# Help Target
help:
@echo "The following are some of the valid targets for this Makefile:"
@echo "... all (the default if no target is provided)"
@echo "... clean"
@echo "... depend"
@echo "... edit_cache"
@echo "... install"
@echo "... install/local"
@echo "... install/strip"
@echo "... list_install_components"
@echo "... rebuild_cache"
@echo "... ChiselBuild"
@echo "... VMain"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain.o"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain.i"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain.s"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Syms.o"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Syms.i"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Syms.s"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0.o"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0.i"
@echo "... CMakeFiles/VMain.dir/VMain.dir/VMain__Trace__0.s"
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@echo "... auto_bind.o"
@echo "... auto_bind.i"
@echo "... auto_bind.s"
@echo "... csrc_nvboard/main.o"
@echo "... csrc_nvboard/main.i"
@echo "... csrc_nvboard/main.s"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated.o"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated.i"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated.s"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_cov.o"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_cov.i"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_cov.s"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.o"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_threads.i"
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@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.o"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.i"
@echo "... nix/store/lyzgj5m2zhsw9m3v1fnzr3dp1z9myyaz-verilator-5.018/share/verilator/include/verilated_vcd_c.s"
.PHONY : help
#=============================================================================
# Special targets to cleanup operation of make.
# Special rule to run CMake to check the build system integrity.
# No rule that depends on this can have commands that come from listfiles
# because they might be regenerated.
cmake_check_build_system:
$(CMAKE_COMMAND) -S$(CMAKE_SOURCE_DIR) -B$(CMAKE_BINARY_DIR) --check-build-system CMakeFiles/Makefile.cmake 0
.PHONY : cmake_check_build_system

View file

@ -3,14 +3,14 @@
#include <cstdlib> #include <cstdlib>
#include <verilated.h> #include <verilated.h>
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#include <Vexample.h> #include <VSwitch.h>
const int MAX_SIM_TIME=100; const int MAX_SIM_TIME=100;
int main(int argc, char **argv, char **env) { int main(int argc, char **argv, char **env) {
int sim_time = 0; int sim_time = 0;
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Vexample *top = new Vexample; VSwitch *top = new VSwitch;
Verilated::traceEverOn(true); Verilated::traceEverOn(true);
VerilatedVcdC *m_trace = new VerilatedVcdC; VerilatedVcdC *m_trace = new VerilatedVcdC;
@ -19,11 +19,11 @@ int main(int argc, char **argv, char **env) {
m_trace->open("waveform.vcd"); m_trace->open("waveform.vcd");
#endif #endif
for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) { for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
CData sw = rand() & 0b11; top->io_sw_0 = rand() % 2;
top->sw = sw; top->io_sw_1 = rand() % 2;
top->eval(); top->eval();
printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr); printf("sw0 = %d, sw1 = %d, ledr = %d\n", top->io_sw_0, top->io_sw_1, top->io_out);
assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) ); assert(top->io_out == (top->io_sw_0 ^ top->io_sw_1));
#ifdef VERILATOR_TRACE #ifdef VERILATOR_TRACE
m_trace->dump(sim_time); m_trace->dump(sim_time);
#endif #endif

View file

@ -3,15 +3,15 @@
#include <cstdlib> #include <cstdlib>
#include <verilated.h> #include <verilated.h>
#include <verilated_vcd_c.h> #include <verilated_vcd_c.h>
#include <Vexample.h>
#include <nvboard.h> #include <nvboard.h>
#include <VSwitch.h>
const int MAX_SIM_TIME=100; const int MAX_SIM_TIME=100;
void nvboard_bind_all_pins(Vexample* top); void nvboard_bind_all_pins(VSwitch* top);
int main(int argc, char **argv, char **env) { int main(int argc, char **argv, char **env) {
Vexample *top = new Vexample; VSwitch *top = new VSwitch;
nvboard_bind_all_pins(top); nvboard_bind_all_pins(top);
nvboard_init(); nvboard_init();

View file

@ -20,11 +20,11 @@
}, },
"nixpkgs": { "nixpkgs": {
"locked": { "locked": {
"lastModified": 1703013332, "lastModified": 1704194953,
"narHash": "sha256-+tFNwMvlXLbJZXiMHqYq77z/RfmpfpiI3yjL6o/Zo9M=", "narHash": "sha256-RtDKd8Mynhe5CFnVT8s0/0yqtWFMM9LmCzXv/YKxnq4=",
"owner": "NixOS", "owner": "NixOS",
"repo": "nixpkgs", "repo": "nixpkgs",
"rev": "54aac082a4d9bb5bbc5c4e899603abfb76a3f6d6", "rev": "bd645e8668ec6612439a9ee7e71f7eac4099d4f6",
"type": "github" "type": "github"
}, },
"original": { "original": {
@ -34,10 +34,31 @@
"type": "github" "type": "github"
} }
}, },
"nur-xin": {
"inputs": {
"nixpkgs": [
"nixpkgs"
]
},
"locked": {
"lastModified": 1704450168,
"narHash": "sha256-zOLL35LX83Of64quCyxpyP8rTSO/tgrfHNm52tFo6VU=",
"ref": "refs/heads/master",
"rev": "beda2a57d946f392d958755c7bb03ac092a20f42",
"revCount": 140,
"type": "git",
"url": "https://git.xinyang.life/xin/nur.git"
},
"original": {
"type": "git",
"url": "https://git.xinyang.life/xin/nur.git"
}
},
"root": { "root": {
"inputs": { "inputs": {
"flake-utils": "flake-utils", "flake-utils": "flake-utils",
"nixpkgs": "nixpkgs" "nixpkgs": "nixpkgs",
"nur-xin": "nur-xin"
} }
}, },
"systems": { "systems": {

View file

@ -2,37 +2,107 @@
inputs = { inputs = {
nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
flake-utils.url = "github:numtide/flake-utils"; flake-utils.url = "github:numtide/flake-utils";
nur-xin = {
url = "git+https://git.xinyang.life/xin/nur.git";
inputs.nixpkgs.follows = "nixpkgs";
};
}; };
outputs = { self, ... }@inputs: with inputs; outputs = { self, ... }@inputs: with inputs;
flake-utils.lib.eachDefaultSystem (system: flake-utils.lib.eachDefaultSystem (system:
let pkgs = nixpkgs.legacyPackages.${system}; in let
pkgs = nixpkgs.legacyPackages.${system} //
{ nur.xin = nur-xin.legacyPackages.${system}; };
in
{ {
devShells.default = pkgs.mkShell { devShells.default = with pkgs; mkShell {
packages = with pkgs; [ packages = [
verilator
gtkwave
gcc
gdb
jq
bear
clang-tools clang-tools
rnix-lsp rnix-lsp
gdb
jre
]; ];
nativeBuildInputs = with pkgs; [ inputsFrom = [ self.packages.${system}.default ];
python3 };
packages.default = with pkgs; clangStdenv.mkDerivation {
name = "npc";
version = "0.0.1";
src = ./.;
nativeBuildInputs = [
cmake
sbt
nur.xin.nvboard
self.packages.${system}.circt
];
buildInputs = [
verilator
nur.xin.nvboard
]; ];
buildInputs = with pkgs; [ NEMU_HOME="/home/xin/repo/ysyx-workbench/nemu";
SDL2 };
SDL2_image
# This version (1.43.0) of circt does not exist in nixpkgs
# and Chisel 5.1.0 specifically build against it, so here we are.
# Ref: https://github.com/NixOS/nixpkgs/blob/b6465c8/pkgs/development/compilers/circt/default.nix
packages.circt =
with pkgs;
let
pythonEnv = python3.withPackages (ps: [ ps.psutil ]);
in
stdenv.mkDerivation rec {
pname = "circt";
version = "1.43.0";
src = fetchFromGitHub {
owner = "llvm";
repo = "circt";
rev = "firtool-${version}";
sha256 = "sha256-RkjigboswLkLgLkgOGahQLIygCkC3Q9rbVw3LqIzREY=";
fetchSubmodules = true;
};
requiredSystemFeatures = [ "big-parallel" ];
nativeBuildInputs = [ cmake ninja git pythonEnv ];
cmakeDir = "../llvm/llvm";
cmakeFlags = [
"-DLLVM_ENABLE_BINDINGS=OFF"
"-DLLVM_ENABLE_OCAMLDOC=OFF"
"-DLLVM_BUILD_EXAMPLES=OFF"
"-DLLVM_OPTIMIZED_TABLEGEN=ON"
"-DLLVM_ENABLE_PROJECTS=mlir"
"-DLLVM_EXTERNAL_PROJECTS=circt"
"-DLLVM_EXTERNAL_CIRCT_SOURCE_DIR=.."
"-DCIRCT_LLHD_SIM_ENABLED=OFF"
]; ];
shellHook = '' LIT_FILTER_OUT = if stdenv.cc.isClang then "CIRCT :: Target/ExportSystemC/.*\.mlir" else null;
export NEMU_HOME=/home/xin/repo/ysyx-workbench/nemu
preConfigure = ''
find ./test -name '*.mlir' -exec sed -i 's|/usr/bin/env|${coreutils}/bin/env|g' {} \;
''; '';
installPhase = ''
runHook preInstall
mkdir -p $out/bin
mv bin/{{fir,hls}tool,circt-{as,dis,lsp-server,opt,reduce,translate}} $out/bin
runHook postInstall
'';
doCheck = true;
checkTarget = "check-circt check-circt-integration";
meta = {
description = "Circuit IR compilers and tools";
homepage = "https://circt.org/";
license = lib.licenses.asl20;
maintainers = with lib.maintainers; [ sharzy ];
platforms = lib.platforms.all;
};
}; };
} }
); );
} }

View file

@ -1,6 +0,0 @@
module top(
input [1:0] sw,
output ledr
);
assign ledr = sw[1] ^ sw[0];
endmodule