> configure(npc)

ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  09:30:12  up   0:20,  2 users,  load average: 2.09, 1.42, 0.86

npc/core/src/main/scala/ALU.scala

@@ -3,21 +3,17 @@ package npc.util
 import chisel3._
 import chisel3.util._
 
-object ALUSel extends ChiselEnum {
+class ALUGenerator(width: Int) extends Module {
-  val add, sub, not, and, or, xor, slt, eq, nop = Value
+  require(width >= 0)
-}
-
-class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module {
   val io = IO(new Bundle {
-    val a = Input(UInt(tpe.getWidth.W))
+    val a = Input(UInt(width.W))
-    val b = Input(UInt(tpe.getWidth.W))
+    val b = Input(UInt(width.W))
-    val op = Input(ALUSel())
+    val op = Input(UInt(4.W))
-    val out = Output(UInt(tpe.getWidth.W))
+    val out = Output(UInt(width.W))
   })
 
-  // val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0)  // take (-b) if sub
+  val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0)  // take (-b) if sub
-  val add = io.a + io.b 
+  val add = io.a + adder_b
-  val sub = io.a - io.b
   val and = io.a & io.b
   val not = ~io.a
   val or = io.a | io.b
@@ -25,14 +21,14 @@ class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module
   val slt = io.a < io.b
   val eq = io.a === io.b
 
-  io.out := MuxLookup(io.op, ALUSel.nop.asUInt)(Seq(
+  io.out := MuxLookup(io.op, 0.U)(Seq(
-    ALUSel.add -> add,
+    0.U -> add,
-    ALUSel.sub -> sub,
+    1.U -> add, // add with b reversed
-    ALUSel.not -> not,
+    2.U -> not,
-    ALUSel.and -> and,
+    3.U -> and,
-    ALUSel.or  -> or,
+    4.U -> or,
-    ALUSel.xor -> xor,
+    5.U -> xor,
-    ALUSel.slt -> slt,
+    6.U -> slt,
-    ALUSel.eq -> eq
+    7.U -> eq,
   ))
 }

npc/core/src/main/scala/Main.scala

@@ -3,12 +3,9 @@ package npc
 import chisel3._
 import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
 import chisel3.util.{SRAM}
-import chisel3.util.experimental.decode.{decoder, TruthTable, QMCMinimizer}
 import chisel3.stage.ChiselOption
-import npc.util.{ KeyboardSegController }
+import npc.util.{ KeyboardSegController, RegisterFile }
-import flowpc.components.RegisterFile
+import flowpc.components.ProgramCounter
-import chisel3.util.log2Ceil
-import chisel3.util.BitPat
 
 class Switch extends Module {
   val io = IO(new Bundle {
@@ -36,51 +33,12 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
-object RV32Inst extends ChiselEnum {
+<<<<<<< Updated upstream
-  val addi = Value("b0010011".U)
+=======
-  val inv = Value("b0000000".U)
-}
-
-object InstType extends ChiselEnum {
-  val R, I, S, B, U, J = Value
-}
-
-class RegControl(width: Int) extends Bundle {
-  object RegWriteDataSel extends ChiselEnum {
-    val ALUOut = Value
-  }
-  val T = RegWriteDataSel
-  val writeEnable = Output(Bool()) 
-  val writeSelect = Output(this.T())
-}
-
-class Control(width: Int) extends Bundle {
-  val inst = IO(Input(UInt(width.W)))
-  val out = decoder(QMCMinimizer, inst, TruthTable(
-    Map(
-      BitPat(Opcode.addi.asUInt) -> BitPat("b00001")
-    ), BitPat("b?????")))
-  val regControl = new RegControl(width)
-
-}
-
 class Flowpc extends Module {
   val io = IO(new Bundle { })
-  val register_file = new RegisterFile(readPorts = 2)
+  val register_file = new RegisterFile(readPorts = 2);
-  val pc = new ProgramCounter(32)
+  val pc = new ProgramCounter(32);
-  val ram = SRAM(size=128*1024*1024, tpe=UInt(32.W), numReadPorts=2, numWritePorts=1,numReadwritePorts=0)
+  val adder = new SRAM()
-
-  // Instruction Fetch
-  ram.readPorts(0).address := pc.io.pc
-  ram.readPorts(0).enable := true.B
-  val instruction = ram.readPorts(0).address
-
-  // Instruction Decode
-  val opcode = Opcode(instruction(7,0))
-
-  // Execution
-
-  // Next PC
-  pc.io.pc_srcs(ProgramCounterSel.selectPC.asUInt) := pc.io.pc + 4.U
-  // pc.io.pc_srcs(ProgramCounterSel.selectResult.asUInt) := 
 }
+>>>>>>> Stashed changes

npc/core/src/main/scala/ProgramCounter.scala

@@ -1,17 +1,11 @@
 package flowpc.components
 import chisel3._
-import chisel3.util.{Valid, log2Ceil}
+import chisel3.util.{Valid}
-import chisel3.util.MuxLookup
-
-object ProgramCounterSel extends ChiselEnum {
-    val selectPC, selectResult = Value
-}
 
 class ProgramCounter (width: Int) extends Module {
   val io = new Bundle {
-    val pc_srcs = Input(Vec(1 << (ProgramCounterSel.getWidth - 1), UInt(width.W)))
+    val next_pc = Input(Flipped(Valid(UInt(width.W))))
-    val select = Input(UInt(ProgramCounterSel.getWidth.W))
     val pc = Output(UInt(width.W))
   }
-    io.pc := io.pc_srcs(io.select)
+    io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc)
 }

npc/core/src/main/scala/RegisterFile.scala

@@ -1,28 +1,25 @@
-package flowpc.components
+package npc.util
 
 import chisel3._
-import chisel3.util.log2Ceil
-import chisel3.util.UIntToOH
 
-class RegisterFile(width: Int, numRegisters: Int, numReadPorts: Int) extends Module {
+class RegisterFile(readPorts: Int) extends Module {
-  require(numReadPorts >= 0)
+  require(readPorts >= 0)
-  val writePort = IO(new Bundle {
+  val io = IO(new Bundle {
-    val enable = Input(Bool())
+    val writeEnable = Input(Bool())
-    val addr = Input(UInt(log2Ceil(width).W))
+    val writeAddr = Input(UInt(5.W))
-    val data = Input(UInt(width.W))
+    val writeData = Input(UInt(32.W))
+    val readAddr = Input(Vec(readPorts, UInt(5.W)))
+    val readData = Output(Vec(readPorts, UInt(32.W)))
   })
-  val readPorts = IO(Vec(numReadPorts, new Bundle {
-    val addr = Input(UInt(log2Ceil(width).W))
-    val data = Output(UInt(width.W))
-  }))
 
-  val regFile = RegInit(VecInit(Seq.fill(numRegisters)(0.U(32.W))))
+  val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
-  val writeAddrOH = UIntToOH(writePort.addr)
+  for (i <- 1 until 32) {
-  for ((reg, i) <- regFile.zipWithIndex) {
+    regFile(i) := regFile(i)
-    reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg)
   }
+  regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
+  regFile(0) := 0.U
 
-  for (readPort <- readPorts) {
+  for (i <- 0 until readPorts) {
-    readPort.data := regFile(readPort.addr)
+    io.readData(i) := regFile(io.readAddr(i))
   }
 }

npc/core/src/test/scala/Main.scala

@@ -60,7 +60,7 @@ class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
       6 -> ((a, b) => if (a < b) 1 else 0),
       7 -> ((a, b) => if (a == b) 1 else 0),
     )
-    val validate = (c: ALUGenerator[32], op: Int, oprands: List[(BigInt, BigInt)]) => {
+    val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
       c.io.op.poke(op.U)
       oprands.foreach({ case (a, b) =>
         c.io.a.poke(a.U)

npc/flake.nix

@@ -19,7 +19,6 @@
           packages = [
             clang-tools
             rnix-lsp
-            coursier
 
             gdb
             jre