diff --git a/npc/core/src/main/scala/ALU.scala b/npc/core/src/main/scala/ALU.scala index 70705d7..65ade3e 100644 --- a/npc/core/src/main/scala/ALU.scala +++ b/npc/core/src/main/scala/ALU.scala @@ -3,21 +3,17 @@ package npc.util import chisel3._ import chisel3.util._ -object ALUSel extends ChiselEnum { - val add, sub, not, and, or, xor, slt, eq, nop = Value -} - -class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module { +class ALUGenerator(width: Int) extends Module { + require(width >= 0) val io = IO(new Bundle { - val a = Input(UInt(tpe.getWidth.W)) - val b = Input(UInt(tpe.getWidth.W)) - val op = Input(ALUSel()) - val out = Output(UInt(tpe.getWidth.W)) + val a = Input(UInt(width.W)) + val b = Input(UInt(width.W)) + val op = Input(UInt(4.W)) + val out = Output(UInt(width.W)) }) - // val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub - val add = io.a + io.b - val sub = io.a - io.b + val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub + val add = io.a + adder_b val and = io.a & io.b val not = ~io.a val or = io.a | io.b @@ -25,14 +21,14 @@ class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module val slt = io.a < io.b val eq = io.a === io.b - io.out := MuxLookup(io.op, ALUSel.nop.asUInt)(Seq( - ALUSel.add -> add, - ALUSel.sub -> sub, - ALUSel.not -> not, - ALUSel.and -> and, - ALUSel.or -> or, - ALUSel.xor -> xor, - ALUSel.slt -> slt, - ALUSel.eq -> eq + io.out := MuxLookup(io.op, 0.U)(Seq( + 0.U -> add, + 1.U -> add, // add with b reversed + 2.U -> not, + 3.U -> and, + 4.U -> or, + 5.U -> xor, + 6.U -> slt, + 7.U -> eq, )) } diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index 9f601e7..95b9e61 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -3,12 +3,9 @@ package npc import chisel3._ import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse} import chisel3.util.{SRAM} -import chisel3.util.experimental.decode.{decoder, TruthTable, QMCMinimizer} import chisel3.stage.ChiselOption -import npc.util.{ KeyboardSegController } -import flowpc.components.RegisterFile -import chisel3.util.log2Ceil -import chisel3.util.BitPat +import npc.util.{ KeyboardSegController, RegisterFile } +import flowpc.components.ProgramCounter class Switch extends Module { val io = IO(new Bundle { @@ -36,51 +33,12 @@ class Keyboard extends Module { io.segs := seg_handler.io.segs } -object RV32Inst extends ChiselEnum { - val addi = Value("b0010011".U) - val inv = Value("b0000000".U) -} - -object InstType extends ChiselEnum { - val R, I, S, B, U, J = Value -} - -class RegControl(width: Int) extends Bundle { - object RegWriteDataSel extends ChiselEnum { - val ALUOut = Value - } - val T = RegWriteDataSel - val writeEnable = Output(Bool()) - val writeSelect = Output(this.T()) -} - -class Control(width: Int) extends Bundle { - val inst = IO(Input(UInt(width.W))) - val out = decoder(QMCMinimizer, inst, TruthTable( - Map( - BitPat(Opcode.addi.asUInt) -> BitPat("b00001") - ), BitPat("b?????"))) - val regControl = new RegControl(width) - -} - +<<<<<<< Updated upstream +======= class Flowpc extends Module { val io = IO(new Bundle { }) - val register_file = new RegisterFile(readPorts = 2) - val pc = new ProgramCounter(32) - val ram = SRAM(size=128*1024*1024, tpe=UInt(32.W), numReadPorts=2, numWritePorts=1,numReadwritePorts=0) - - // Instruction Fetch - ram.readPorts(0).address := pc.io.pc - ram.readPorts(0).enable := true.B - val instruction = ram.readPorts(0).address - - // Instruction Decode - val opcode = Opcode(instruction(7,0)) - - // Execution - - // Next PC - pc.io.pc_srcs(ProgramCounterSel.selectPC.asUInt) := pc.io.pc + 4.U - // pc.io.pc_srcs(ProgramCounterSel.selectResult.asUInt) := + val register_file = new RegisterFile(readPorts = 2); + val pc = new ProgramCounter(32); + val adder = new SRAM() } +>>>>>>> Stashed changes diff --git a/npc/core/src/main/scala/ProgramCounter.scala b/npc/core/src/main/scala/ProgramCounter.scala index 056cd5b..0687f9a 100644 --- a/npc/core/src/main/scala/ProgramCounter.scala +++ b/npc/core/src/main/scala/ProgramCounter.scala @@ -1,17 +1,11 @@ package flowpc.components import chisel3._ -import chisel3.util.{Valid, log2Ceil} -import chisel3.util.MuxLookup - -object ProgramCounterSel extends ChiselEnum { - val selectPC, selectResult = Value -} +import chisel3.util.{Valid} class ProgramCounter (width: Int) extends Module { val io = new Bundle { - val pc_srcs = Input(Vec(1 << (ProgramCounterSel.getWidth - 1), UInt(width.W))) - val select = Input(UInt(ProgramCounterSel.getWidth.W)) + val next_pc = Input(Flipped(Valid(UInt(width.W)))) val pc = Output(UInt(width.W)) } - io.pc := io.pc_srcs(io.select) + io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc) } diff --git a/npc/core/src/main/scala/RegisterFile.scala b/npc/core/src/main/scala/RegisterFile.scala index 8bb3cc0..fbf8a94 100644 --- a/npc/core/src/main/scala/RegisterFile.scala +++ b/npc/core/src/main/scala/RegisterFile.scala @@ -1,28 +1,25 @@ -package flowpc.components +package npc.util import chisel3._ -import chisel3.util.log2Ceil -import chisel3.util.UIntToOH -class RegisterFile(width: Int, numRegisters: Int, numReadPorts: Int) extends Module { - require(numReadPorts >= 0) - val writePort = IO(new Bundle { - val enable = Input(Bool()) - val addr = Input(UInt(log2Ceil(width).W)) - val data = Input(UInt(width.W)) +class RegisterFile(readPorts: Int) extends Module { + require(readPorts >= 0) + val io = IO(new Bundle { + val writeEnable = Input(Bool()) + val writeAddr = Input(UInt(5.W)) + val writeData = Input(UInt(32.W)) + val readAddr = Input(Vec(readPorts, UInt(5.W))) + val readData = Output(Vec(readPorts, UInt(32.W))) }) - val readPorts = IO(Vec(numReadPorts, new Bundle { - val addr = Input(UInt(log2Ceil(width).W)) - val data = Output(UInt(width.W)) - })) - val regFile = RegInit(VecInit(Seq.fill(numRegisters)(0.U(32.W)))) - val writeAddrOH = UIntToOH(writePort.addr) - for ((reg, i) <- regFile.zipWithIndex) { - reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg) + val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W)))) + for (i <- 1 until 32) { + regFile(i) := regFile(i) } + regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr)) + regFile(0) := 0.U - for (readPort <- readPorts) { - readPort.data := regFile(readPort.addr) + for (i <- 0 until readPorts) { + io.readData(i) := regFile(io.readAddr(i)) } } diff --git a/npc/core/src/test/scala/Main.scala b/npc/core/src/test/scala/Main.scala index 51fa284..c9c093e 100644 --- a/npc/core/src/test/scala/Main.scala +++ b/npc/core/src/test/scala/Main.scala @@ -60,7 +60,7 @@ class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester { 6 -> ((a, b) => if (a < b) 1 else 0), 7 -> ((a, b) => if (a == b) 1 else 0), ) - val validate = (c: ALUGenerator[32], op: Int, oprands: List[(BigInt, BigInt)]) => { + val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => { c.io.op.poke(op.U) oprands.foreach({ case (a, b) => c.io.a.poke(a.U) diff --git a/npc/flake.nix b/npc/flake.nix index e62173c..32aa36a 100644 --- a/npc/flake.nix +++ b/npc/flake.nix @@ -19,7 +19,6 @@ packages = [ clang-tools rnix-lsp - coursier gdb jre