> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar 1 12:35:11 UTC 2024 x86_64 GNU/Linux 09:30:12 up 0:20, 2 users, load average: 2.09, 1.42, 0.86
This commit is contained in:
tracer-ysyx
parent
1e10f8a249
commit
147014c8fa
6 changed files with 45 additions and 101 deletions
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@ -3,21 +3,17 @@ package npc.util
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import chisel3._
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import chisel3.util._
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object ALUSel extends ChiselEnum {
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val add, sub, not, and, or, xor, slt, eq, nop = Value
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}
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class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module {
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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val io = IO(new Bundle {
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val a = Input(UInt(tpe.getWidth.W))
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val b = Input(UInt(tpe.getWidth.W))
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val op = Input(ALUSel())
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val out = Output(UInt(tpe.getWidth.W))
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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})
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// val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + io.b
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val sub = io.a - io.b
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val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + adder_b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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@ -25,14 +21,14 @@ class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module
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val slt = io.a < io.b
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val eq = io.a === io.b
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io.out := MuxLookup(io.op, ALUSel.nop.asUInt)(Seq(
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ALUSel.add -> add,
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ALUSel.sub -> sub,
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ALUSel.not -> not,
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ALUSel.and -> and,
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ALUSel.or -> or,
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ALUSel.xor -> xor,
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ALUSel.slt -> slt,
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ALUSel.eq -> eq
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io.out := MuxLookup(io.op, 0.U)(Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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))
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}
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@ -3,12 +3,9 @@ package npc
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import chisel3._
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.util.{SRAM}
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import chisel3.util.experimental.decode.{decoder, TruthTable, QMCMinimizer}
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import chisel3.stage.ChiselOption
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import npc.util.{ KeyboardSegController }
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import flowpc.components.RegisterFile
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import chisel3.util.log2Ceil
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import chisel3.util.BitPat
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import npc.util.{ KeyboardSegController, RegisterFile }
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import flowpc.components.ProgramCounter
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class Switch extends Module {
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val io = IO(new Bundle {
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@ -36,51 +33,12 @@ class Keyboard extends Module {
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io.segs := seg_handler.io.segs
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}
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object RV32Inst extends ChiselEnum {
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val addi = Value("b0010011".U)
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val inv = Value("b0000000".U)
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}
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object InstType extends ChiselEnum {
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val R, I, S, B, U, J = Value
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}
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class RegControl(width: Int) extends Bundle {
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object RegWriteDataSel extends ChiselEnum {
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val ALUOut = Value
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}
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val T = RegWriteDataSel
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val writeEnable = Output(Bool())
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val writeSelect = Output(this.T())
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}
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class Control(width: Int) extends Bundle {
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val inst = IO(Input(UInt(width.W)))
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val out = decoder(QMCMinimizer, inst, TruthTable(
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Map(
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BitPat(Opcode.addi.asUInt) -> BitPat("b00001")
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), BitPat("b?????")))
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val regControl = new RegControl(width)
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}
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<<<<<<< Updated upstream
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=======
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class Flowpc extends Module {
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val io = IO(new Bundle { })
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val register_file = new RegisterFile(readPorts = 2)
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val pc = new ProgramCounter(32)
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val ram = SRAM(size=128*1024*1024, tpe=UInt(32.W), numReadPorts=2, numWritePorts=1,numReadwritePorts=0)
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// Instruction Fetch
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ram.readPorts(0).address := pc.io.pc
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ram.readPorts(0).enable := true.B
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val instruction = ram.readPorts(0).address
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// Instruction Decode
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val opcode = Opcode(instruction(7,0))
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// Execution
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// Next PC
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pc.io.pc_srcs(ProgramCounterSel.selectPC.asUInt) := pc.io.pc + 4.U
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// pc.io.pc_srcs(ProgramCounterSel.selectResult.asUInt) :=
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val register_file = new RegisterFile(readPorts = 2);
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val pc = new ProgramCounter(32);
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val adder = new SRAM()
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}
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>>>>>>> Stashed changes
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@ -1,17 +1,11 @@
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package flowpc.components
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import chisel3._
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import chisel3.util.{Valid, log2Ceil}
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import chisel3.util.MuxLookup
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object ProgramCounterSel extends ChiselEnum {
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val selectPC, selectResult = Value
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}
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import chisel3.util.{Valid}
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class ProgramCounter (width: Int) extends Module {
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val io = new Bundle {
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val pc_srcs = Input(Vec(1 << (ProgramCounterSel.getWidth - 1), UInt(width.W)))
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val select = Input(UInt(ProgramCounterSel.getWidth.W))
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val next_pc = Input(Flipped(Valid(UInt(width.W))))
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val pc = Output(UInt(width.W))
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}
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io.pc := io.pc_srcs(io.select)
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io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc)
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}
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@ -1,28 +1,25 @@
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package flowpc.components
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package npc.util
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import chisel3._
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import chisel3.util.log2Ceil
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import chisel3.util.UIntToOH
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class RegisterFile(width: Int, numRegisters: Int, numReadPorts: Int) extends Module {
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require(numReadPorts >= 0)
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val writePort = IO(new Bundle {
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val enable = Input(Bool())
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val addr = Input(UInt(log2Ceil(width).W))
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val data = Input(UInt(width.W))
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val readPorts = IO(Vec(numReadPorts, new Bundle {
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val addr = Input(UInt(log2Ceil(width).W))
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val data = Output(UInt(width.W))
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}))
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val regFile = RegInit(VecInit(Seq.fill(numRegisters)(0.U(32.W))))
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val writeAddrOH = UIntToOH(writePort.addr)
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for ((reg, i) <- regFile.zipWithIndex) {
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reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg)
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (readPort <- readPorts) {
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readPort.data := regFile(readPort.addr)
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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@ -60,7 +60,7 @@ class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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6 -> ((a, b) => if (a < b) 1 else 0),
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7 -> ((a, b) => if (a == b) 1 else 0),
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)
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val validate = (c: ALUGenerator[32], op: Int, oprands: List[(BigInt, BigInt)]) => {
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val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
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c.io.op.poke(op.U)
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oprands.foreach({ case (a, b) =>
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c.io.a.poke(a.U)
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@ -19,7 +19,6 @@
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packages = [
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clang-tools
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rnix-lsp
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coursier
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gdb
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jre
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