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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  11:40:05  up   1:16,  2 users,  load average: 0.90, 0.86, 0.79
This commit is contained in:
tracer-ysyx 2024-03-13 11:40:05 +08:00 committed by xinyangli
parent 2a27cd71c7
commit 110d8d5288
3 changed files with 278 additions and 16 deletions
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28
npc/core/src/main/scala/ALU.scala
View file

@ -8,33 +8,39 @@ class ALUControlInterface extends Bundle {
object OpSelect extends ChiselEnum { object OpSelect extends ChiselEnum {
val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
} }
object SrcSelect extends ChiselEnum {
val aSrcRs2, aSrcImm = Value
}
val op = Input(OpSelect()) val op = Input(OpSelect())
val src = Input(SrcSelect())
type CtrlTypes = OpSelect.Type :: HNil type CtrlTypes = OpSelect.Type :: SrcSelect.Type :: HNil
def ctrlBindPorts: CtrlTypes = { def ctrlBindPorts: CtrlTypes = {
op :: HNil op :: src :: HNil
} }
} }
class ALU[T <: UInt](tpe: T) extends Module { class ALU[T <: UInt](tpe: T) extends Module {
val control = IO(new ALUControlInterface) val control = IO(new ALUControlInterface)
val in = IO(new Bundle { val in = IO(new Bundle {
val a = Input(tpe) val a = Input(Vec(control.SrcSelect.getWidth, tpe))
val b = Input(tpe) val b = Input(tpe)
}) })
val out = IO(new Bundle { val out = IO(new Bundle {
val result = Output(tpe) val result = Output(tpe)
}) })
val a = in.a(control.src.asUInt)
// val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub // val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
val add = in.a + in.b val add = a + in.b
val sub = in.a - in.b val sub = a - in.b
val and = in.a & in.b val and = a & in.b
val not = ~in.a val not = ~a
val or = in.a | in.b val or = a | in.b
val xor = in.a ^ in.b val xor = a ^ in.b
val slt = in.a < in.b val slt = a < in.b
val eq = in.a === in.b val eq = a === in.b
import control.OpSelect._ import control.OpSelect._

9
npc/core/src/main/scala/Main.scala
View file

@ -38,23 +38,25 @@ class Control(width: Int) extends Module {
// TODO: Add .ctrlTypes together instead of writing them by hand. // TODO: Add .ctrlTypes together instead of writing them by hand.
type T = type T =
Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: HNil Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil
val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts
import reg.WriteSelect._ import reg.WriteSelect._
import pc.SrcSelect._ import pc.SrcSelect._
import alu.OpSelect._ import alu.OpSelect._
import alu.SrcSelect._
import RV32Inst._ import RV32Inst._
val ControlMapping: Array[(BitPat, T)] = Array( val ControlMapping: Array[(BitPat, T)] = Array(
// Regs :: PC :: Exe // Regs :: PC :: Exe
// writeEnable :: writeSelect :: srcSelect :: // writeEnable :: writeSelect :: srcSelect ::
(addi, false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil), (addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil),
) )
println(ControlMapping)
def toBits(t: T): BitPat = { def toBits(t: T): BitPat = {
val list: List[Data] = t.toList val list: List[Data] = t.toList
list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _) list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _)
} }
val default = BitPat("b???????") val default = BitPat("b????????")
reg.writeEnable := false.B reg.writeEnable := false.B
reg.writeSelect := reg.WriteSelect(0.U) reg.writeSelect := reg.WriteSelect(0.U)
@ -126,6 +128,5 @@ class Flow extends Module {
alu.in.a := reg.out.src(0) alu.in.a := reg.out.src(0)
alu.in.b := reg.out.src(1) alu.in.b := reg.out.src(1)
printf("Yes\n")
dontTouch(control.out) dontTouch(control.out)
} }

257
npc/waveform.vcd
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@ -125,108 +125,363 @@ b00000000000000000000000000000000 I
b00000000000000000000000000000000 J b00000000000000000000000000000000 J
b00000000000000000000000000000000 K b00000000000000000000000000000000 K
b00000000000000000000000000000000 L b00000000000000000000000000000000 L
0M 1M
0N 0N
b0000 O b0000 O
0P 0P
b0000000 Q b0000000 Q
1R 1R
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b00000000000000000000000000000100 '
b0000000100 (
b00000000000010000100000100010011 )
b00010 *
b10000 +
0M
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b00000000000000000000000000001000 '
b0000001000 (
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b0000001100 (
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b00000000000000000000000000010100 &
b00000000000000000000000000010000 '
b0000010000 (
b00000000000000000000000000000000 )
b00000 *
b00000 +
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b00000000000000000000000000010100 '
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