From 110d8d5288c2530026574c32d4686a795fd1c732 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Wed, 13 Mar 2024 11:40:05 +0800 Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?= =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.6.19=20#1-?= =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:11?= =?UTF-8?q?=20UTC=202024=20x86=5F64=20GNU/Linux=20=20=2011:40:05=20=20up?= =?UTF-8?q?=20=20=201:16,=20=202=20users,=20=20load=20average:=200.90,=200?= =?UTF-8?q?.86,=200.79?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/ALU.scala | 28 ++-- npc/core/src/main/scala/Main.scala | 9 +- npc/waveform.vcd | 257 ++++++++++++++++++++++++++++- 3 files changed, 278 insertions(+), 16 deletions(-) diff --git a/npc/core/src/main/scala/ALU.scala b/npc/core/src/main/scala/ALU.scala index b391c3a..a5cae78 100644 --- a/npc/core/src/main/scala/ALU.scala +++ b/npc/core/src/main/scala/ALU.scala @@ -8,33 +8,39 @@ class ALUControlInterface extends Bundle { object OpSelect extends ChiselEnum { val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value } + object SrcSelect extends ChiselEnum { + val aSrcRs2, aSrcImm = Value + } val op = Input(OpSelect()) + val src = Input(SrcSelect()) - type CtrlTypes = OpSelect.Type :: HNil + type CtrlTypes = OpSelect.Type :: SrcSelect.Type :: HNil def ctrlBindPorts: CtrlTypes = { - op :: HNil + op :: src :: HNil } } class ALU[T <: UInt](tpe: T) extends Module { val control = IO(new ALUControlInterface) val in = IO(new Bundle { - val a = Input(tpe) + val a = Input(Vec(control.SrcSelect.getWidth, tpe)) val b = Input(tpe) }) val out = IO(new Bundle { val result = Output(tpe) }) + val a = in.a(control.src.asUInt) + // val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub - val add = in.a + in.b - val sub = in.a - in.b - val and = in.a & in.b - val not = ~in.a - val or = in.a | in.b - val xor = in.a ^ in.b - val slt = in.a < in.b - val eq = in.a === in.b + val add = a + in.b + val sub = a - in.b + val and = a & in.b + val not = ~a + val or = a | in.b + val xor = a ^ in.b + val slt = a < in.b + val eq = a === in.b import control.OpSelect._ diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index b56b939..3b21302 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -38,23 +38,25 @@ class Control(width: Int) extends Module { // TODO: Add .ctrlTypes together instead of writing them by hand. type T = - Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: HNil + Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts import reg.WriteSelect._ import pc.SrcSelect._ import alu.OpSelect._ + import alu.SrcSelect._ import RV32Inst._ val ControlMapping: Array[(BitPat, T)] = Array( // Regs :: PC :: Exe // writeEnable :: writeSelect :: srcSelect :: - (addi, false.B :: rAluOut :: pStaticNpc :: aOpAdd :: HNil), + (addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil), ) + println(ControlMapping) def toBits(t: T): BitPat = { val list: List[Data] = t.toList list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _) } - val default = BitPat("b???????") + val default = BitPat("b????????") reg.writeEnable := false.B reg.writeSelect := reg.WriteSelect(0.U) @@ -126,6 +128,5 @@ class Flow extends Module { alu.in.a := reg.out.src(0) alu.in.b := reg.out.src(1) - printf("Yes\n") dontTouch(control.out) } diff --git a/npc/waveform.vcd b/npc/waveform.vcd index 6592a48..e978c4b 100644 --- a/npc/waveform.vcd +++ b/npc/waveform.vcd @@ -125,108 +125,363 @@ b00000000000000000000000000000000 I b00000000000000000000000000000000 J b00000000000000000000000000000000 K b00000000000000000000000000000000 L -0M +1M 0N b0000 O 0P b0000000 Q 1R #1 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