xin/ysyx-workbench
1
0
Fork 0
Code Issues Pull requests 1 Projects Releases Packages Wiki Activity Actions

> configure(npc)

Browse source 
ysyx_22040000 李心杨
 Linux calcite 6.6.18 #1-NixOS SMP PREEMPT_DYNAMIC Fri Feb 23 08:25:28 UTC 2024 x86_64 GNU/Linux
  13:40:50  up 2 days 17:09,  2 users,  load average: 0.63, 0.60, 0.73
This commit is contained in:
tracer-ysyx 2024-03-07 13:40:50 +08:00 committed by xinyangli
parent 035a1e5cff
commit 0be92d4c44
3 changed files with 4 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
nemu/src/isa/riscv32/inst.c
View file

@ -59,21 +59,6 @@ static void do_branch(Decode *s, bool condition, word_t offset) {
} }
} }
// static word_t mulh(word_t src1, word_t src2) {
// word_t split_width = (WORD_BYTES * 8 / 2);
// word_t split_low_mask = (1u << split_width) - 1;
// word_t src1_lo = src1 & split_low_mask;
// word_t src1_hi = src1 >> split_width;
// word_t src2_lo = src2 & split_low_mask;
// word_t src2_hi = src2 >> split_width;
// word_t carry_bit = ((src1_hi * src2_lo & split_low_mask) +
// (src1_lo * src2_hi & split_low_mask) +
// (src1_lo * src2_lo >> split_width)) >>
// split_width;
// return src1_hi * src2_hi + (src1_hi * src2_lo >> split_width) +
// (src1_lo * src2_hi >> split_width) + carry_bit;
// }
static int decode_exec(Decode *s) { static int decode_exec(Decode *s) {
int rd = 0; int rd = 0;
word_t src1 = 0, src2 = 0, imm = 0; word_t src1 = 0, src2 = 0, imm = 0;

3
npc/core/src/main/scala/Main.scala
View file

@ -31,3 +31,6 @@ class Keyboard extends Module {
io.segs := seg_handler.io.segs io.segs := seg_handler.io.segs
} }
class Flowpc extends Module {
}

2
npc/core/src/main/scala/RegisterFile.scala
View file

@ -2,7 +2,7 @@ package npc.util
import chisel3._ import chisel3._
class RegisterFile(readPorts: Int) extends Module { class RegisterFile(readPorts: Int = 1) extends Module {
require(readPorts >= 0) require(readPorts >= 0)
val io = IO(new Bundle { val io = IO(new Bundle {
val writeEnable = Input(Bool()) val writeEnable = Input(Bool())