From 0be92d4c44159815e5cfe052f1594a3e1030f571 Mon Sep 17 00:00:00 2001
From: tracer-ysyx <tracer@ysyx.org>
Date: Thu, 7 Mar 2024 13:40:50 +0800
Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?=
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---
 nemu/src/isa/riscv32/inst.c                | 15 ---------------
 npc/core/src/main/scala/Main.scala         |  3 +++
 npc/core/src/main/scala/RegisterFile.scala |  2 +-
 3 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/nemu/src/isa/riscv32/inst.c b/nemu/src/isa/riscv32/inst.c
index e3326c6..9c86937 100644
--- a/nemu/src/isa/riscv32/inst.c
+++ b/nemu/src/isa/riscv32/inst.c
@@ -59,21 +59,6 @@ static void do_branch(Decode *s, bool condition, word_t offset) {
   }
 }
 
-// static word_t mulh(word_t src1, word_t src2) {
-//   word_t split_width = (WORD_BYTES * 8 / 2);
-//   word_t split_low_mask = (1u << split_width) - 1;
-//   word_t src1_lo = src1 & split_low_mask;
-//   word_t src1_hi = src1 >> split_width;
-//   word_t src2_lo = src2 & split_low_mask;
-//   word_t src2_hi = src2 >> split_width;
-//   word_t carry_bit = ((src1_hi * src2_lo & split_low_mask) +
-//                       (src1_lo * src2_hi & split_low_mask) +
-//                       (src1_lo * src2_lo >> split_width)) >>
-//                      split_width;
-//   return src1_hi * src2_hi + (src1_hi * src2_lo >> split_width) +
-//          (src1_lo * src2_hi >> split_width) + carry_bit;
-// }
-
 static int decode_exec(Decode *s) {
   int rd = 0;
   word_t src1 = 0, src2 = 0, imm = 0;
diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index c06bc8e..656cbd4 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -31,3 +31,6 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
+class Flowpc extends Module {
+
+}
diff --git a/npc/core/src/main/scala/RegisterFile.scala b/npc/core/src/main/scala/RegisterFile.scala
index fbf8a94..c6f9229 100644
--- a/npc/core/src/main/scala/RegisterFile.scala
+++ b/npc/core/src/main/scala/RegisterFile.scala
@@ -2,7 +2,7 @@ package npc.util
 
 import chisel3._
 
-class RegisterFile(readPorts: Int) extends Module {
+class RegisterFile(readPorts: Int = 1) extends Module {
   require(readPorts >= 0)
   val io = IO(new Bundle {
     val writeEnable = Input(Bool())