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97df569747
ysyx-workbench
/
npc
/
vsrc
/
example.v
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create Makefile for example in verilator manual
2023-12-23 12:23:18 +00:00
module
top
(
input
a
,
input
b
,
output
f
)
;
assign
f
=
a
^
b
;
endmodule
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