xinyangli
2824efad33
NJU-ProjectN/nemu eb63cf3568dbf4e0c3c6ef462e6ec685550fabbc Merge pull request #76 from rijuyuezhu/master
40 lines
1.5 KiB
C
40 lines
1.5 KiB
C
/***************************************************************************************
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* Copyright (c) 2014-2022 Zihao Yu, Nanjing University
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*
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* NEMU is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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*
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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*
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* See the Mulan PSL v2 for more details.
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***************************************************************************************/
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#ifndef __DIFFTEST_DEF_H__
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#define __DIFFTEST_DEF_H__
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#include <stdint.h>
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#include <macro.h>
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#include <generated/autoconf.h>
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#define __EXPORT __attribute__((visibility("default")))
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enum { DIFFTEST_TO_DUT, DIFFTEST_TO_REF };
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#if defined(CONFIG_ISA_x86)
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# define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 9) // GPRs + pc
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#elif defined(CONFIG_ISA_mips32)
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# define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 38) // GPRs + status + lo + hi + badvaddr + cause + pc
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#elif defined(CONFIG_ISA_riscv)
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#define RISCV_GPR_TYPE MUXDEF(CONFIG_RV64, uint64_t, uint32_t)
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#define RISCV_GPR_NUM MUXDEF(CONFIG_RVE , 16, 32)
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#define DIFFTEST_REG_SIZE (sizeof(RISCV_GPR_TYPE) * (RISCV_GPR_NUM + 1)) // GPRs + pc
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#elif defined(CONFIG_ISA_loongarch32r)
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# define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 33) // GPRs + pc
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#else
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# error Unsupport ISA
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#endif
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#endif
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