ysyx-workbench/npc/Makefile
tracer-ysyx ceb06fd70c > trace RTL
ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 20:12:41  up  23:10,  2 users,  load average: 0.26, 0.52, 0.57
2023-12-23 20:12:41 +08:00

33 lines
862 B
Makefile

VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
PREFIX ?= build
OBJDIR := $(PREFIX)/obj
SUBMAKE := $(OBJDIR)/Vexample.mk
VERILATOR_FLAGS := --cc --exe
all: sim
sim: $(OBJDIR) $(VSRC) $(CPPSRC) $(SUBMAKE)
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample
trace: VERILATOR_FLAGS += --trace
trace: $(OBJDIR) $(VSRC) $(CPPSRC) $(SUBMAKE)
$(call git_commit, "trace RTL") # DO NOT REMOVE THIS LINE!!!
@$(OBJDIR)/Vexample
$(SUBMAKE): $(VSRC) $(CPPSRC)
verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile
.PHONY: clean
clean:
$(RM) -r $(OBJDIR)