ysyx-workbench/npc/obj/Vexample___024root.h
tracer-ysyx df992995ca > sim RTL
ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 18:31:48  up  21:29,  2 users,  load average: 1.18, 0.83, 0.63
2023-12-23 18:31:48 +08:00

42 lines
1 KiB
C++

// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vexample.h for the primary calling header
#ifndef VERILATED_VEXAMPLE___024ROOT_H_
#define VERILATED_VEXAMPLE___024ROOT_H_ // guard
#include "verilated.h"
class Vexample__Syms;
class alignas(VL_CACHE_LINE_BYTES) Vexample___024root final : public VerilatedModule {
public:
// DESIGN SPECIFIC STATE
VL_IN8(a,0,0);
VL_IN8(b,0,0);
VL_OUT8(f,0,0);
CData/*0:0*/ __VstlFirstIteration;
CData/*0:0*/ __VicoFirstIteration;
CData/*0:0*/ __VactContinue;
IData/*31:0*/ __VactIterCount;
VlTriggerVec<1> __VstlTriggered;
VlTriggerVec<1> __VicoTriggered;
VlTriggerVec<0> __VactTriggered;
VlTriggerVec<0> __VnbaTriggered;
// INTERNAL VARIABLES
Vexample__Syms* const vlSymsp;
// CONSTRUCTORS
Vexample___024root(Vexample__Syms* symsp, const char* v__name);
~Vexample___024root();
VL_UNCOPYABLE(Vexample___024root);
// INTERNAL METHODS
void __Vconfigure(bool first);
};
#endif // guard